Pericom Semiconductor 6.2.16. INTERRUPT PIN REGISTER – OFFS" />
參數(shù)資料
型號: PI7C9X7952AFDE
廠商: Pericom
文件頁數(shù): 21/68頁
文件大?。?/td> 0K
描述: IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: PCIe至UART橋接
接口: 高級配置電源接口(ACPI)
電源電壓: 1.8V, 3.3V
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 28 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.16. INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Interrupt Pin
RO
Identifies the legacy interrupt Message(s) the device uses.
Reset to 01h.
6.2.17. POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 01h to indicate that these are power management enhanced
capability registers.
6.2.18. NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
The pointer points to the Power Management capability register
(8Ch).
Reset to 8Ch.
6.2.19. POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Power Management
Revision
RO
Read as 011b to indicate the I/O bridge is compliant to Revision 1.1
of PCI Power Management Interface Specifications.
19
PME# Clock
RO
Does not apply to PCI Express. Must be hardwired to 0b.
20
Auxiliary Power
RO
Read as 1b to indicate the I/O bridge forwards the PME# message in
D3cold and an auxiliary power source is required.
21
Device Specific
Initialization
RO
Read as 0b to indicate the I/O bridge does not have device specific
initialization requirements. The default value may be changed by
auto-loading from EEPROM.
24:22
AUX Current
RO
Reset as 111b to indicate the I/O bridge need 375 mA in D3 state.
The default value may be changed by auto-loading from EEPROM.
25
D1 Power State
Support
RO
Read as 1b to indicate the I/O bridge supports the D1 power
management state. The default value may be changed by
auto-loading from EEPROM.
26
D2 Power State
Support
RO
Read as 1b to indicate the I/O bridge supports the D2 power
management state. The default value may be changed by
auto-loading from EEPROM.
31:27
PME# Support
RO
Read as 01000b to indicate the I/O bridge supports the forwarding of
PME# message in all power states. The default value may be
changed by auto-loading from EEPROM.
6.2.20. POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Power State
RW
Indicates the current power state of the I/O bridge. Writing a value of
D0 causes a hot reset without asserting PEREST_L when the
previous state was D3.
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
2
Reserved
RO
Read as 0b.
3
No_Soft_Reset
RO
When set, this bit indicates that I/O bridge transitioning from D3hot
to D0 does not perform an internal reset.
When clear, an internal reset is performed when power state transits
from D3hot to D0. The default value may be changed by
13-0092
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