參數(shù)資料
型號: PM5352-B1
英文描述: Interface IC
中文描述: 接口IC
文件頁數(shù): 18/77頁
文件大小: 901K
代理商: PM5352-B1
PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
6.2 Section and Line Status DCC Signals
Pin Name
Type
Pin
No.
Function
RSD
Output
AB18
The receive section DCC (RSD) signal contains the
section data communications channel (D1-D3)
The receive section DCC clock (RSDCLK) is used
to clock out the section DCC.
RSDCLK is a 192 kHz clock used to update the
RSD output. RSDCLK is generated by gapping a
216 kHz clock.
The transmit section DCC (TSD) signal contains the
section data communications channel (D1-D3).
TSD is sampled on the rising edge of TSDCLK.
The transmit section DCC clock (TSDCLK) is used
to clock in the section DCC.
TSDCLK is a 192 kHz clock used to sample the
TSD input. TSDCLK is generated by gapping a 216
kHz clock.
RSDCLK
Output
AC21
TSD
Input
AB7
TSDCLK
Output
AA10
RLD
Output
AA16
The receive line DCC (RLD) signal contains the line
data communications channel (D4-D12).
RLDCLK
Output
AB19
The receive line DCC clock (RLDCLK) is used to
clock out the line DCC.
RLDCLK is a 576 kHz clock used to update the
RLD output. RLDCLK is generated by gapping a
2.16 MHz clock.
TLD
Input
AA9
The transmit line DCC (TLD) signal contains the
line data communications channel (D4-D12).
TLD is sampled on the rising edge of TLDCLK.
TLDCLK
Output
AA11
The transmit line DCC clock (TLDCLK) is used to
clock in the line DCC.
TLDCLK is a 576 kHz clock used to sample the
TLD input. TLDCLK is generated by gapping a 2.16
MHz clock.
This Material Copyrighted by Its Respective Manufacturer
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