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參數(shù)資料
| 型號： | PM5352-B1 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 35/77頁 |
| 文件大?。?/td> | 901K |
| 代理商： | PM5352-B1 |
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PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
Pin Name
Type
Pin
No.
Function
RVAL
Output
(POS)
M22
POS-PHY Receive Data Valid (RVAL).
RVAL indicates the validity of the receive data
signals. When RVAL is high, the Receive signals
(RDAT, RSOP, REOP, RMOD, RPRTY and RERR)
are valid. When RVAL is low, all Receive signals are
invalid and must be disregarded. RVAL will
transition low on a FIFO empty condition or on an
end of packet. . No data will be removed from the
receive FIFO while RVAL is deasserted. Once
deasserted, RVAL will remain deasserted until the
current PHY is deselected.
RVAL allows to monitor the selected PHY during a
data transfer, while monitoring other PHY’s is done
using DRPA.
RVAL is tristated when RENB is deasserted. RVAL
is also tristated when either the null-PHY address
(0x7H) or an address not matching the PHY layer
device address is presented on the RADR[2:0]
signals.
RVAL is updated on the rising edge of RFCLK.
UTOPIA Receive FIFO Read Clock (RFCLK).
RFCLK is used to read ATM cells from the receive
FIFO’s. RFCLK must cycle at a 50 MHz or lower
instantaneous rate, but at a high enough rate to
avoid FIFO overflows.
POS-PHY Receive FIFO Read Clock (RFCLK).
This signal is used to read packets from the receive
FIFO’s. RFCLK must cycle at a 50 MHz or lower
instantaneous rate, but at a high enough rate to
avoid FIFO overflows.
RFCLK
Input
(ATM)
P21
RFCLK
Input
(ATM)
P21
This Material Copyrighted by Its Respective Manufacturer
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相關代理商/技術參數(shù) |
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| PM5352-BI | 制造商:PMC 制造商全稱:PMC 功能描述:SATURN USER NETWORK INTERFACE 155 (STAR) |
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| PM5355-SI | 制造商:PMC Sierra from Components Direct 功能描述:PM5355-SI - Trays 制造商:PMC-Sierra 功能描述:PMC-Sierra PM5355-SI ATM UNI |
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