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參數(shù)資料
| 型號： | PM5352-B1 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 25/77頁 |
| 文件大?。?/td> | 901K |
| 代理商： | PM5352-B1 |
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PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
Pin Name
Type
Pin
No.
Function
STPA
Output
(POS)
B19
POS-PHY Selected multi-PHY Transmit Packet
Available (STPA) signal.
STPA transitions high when a predefined
(TPAHWM[7:0] register bits) minimum number of
bytes is available in the selected transmit FIFO (the
FIFO that data is written into). Once high, STPA
indicates that the transmit FIFO is not full. When
STPA transitions low, it optionally indicates that the
transmit FIFO is full or near full (TPALWM[7:0]
register bits). STPA always provide status
indication for the selected PHY in order to avoid
FIFO overflows while polling is performed.
The PHY Layer device shall tristate STPA when
TENB is deasserted. STPA shall also be tristated
when either the null-PHY address (0x7H) or an
address not matching the address set by
PHY_ADR[2:0] is presented on the TADR[2:0]
signals when TENB is sampled high (deasserted
during the previous clock cycle).
STPA is only available in POS-PHY packet-level
transfer mode, as selected by the POS_PLVL
register bit. STPA is tristated in byte-level transfer
mode. STPA is updated on the rising edge of
TFCLK.
UTOPIA Transmit FIFO Write Clock (TFCLK).
This signal is used to write ATM cells to the four cell
transmit FIFOs.
TFCLK cycles at a 50 MHz or lower instantaneous
rate.
POS-PHY Transmit FIFO Write Clock (TFCLK).
This signal is used to write packet octets into the
256 bytes packet FIFO’s.
TFCLK cycles at a 50 MHz or lower instantaneous
rate.
TFCLK
Input
(ATM)
K20
TFCLK
Input
(POS)
K20
This Material Copyrighted by Its Respective Manufacturer
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