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參數(shù)資料
| 型號： | PM5352-B1 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 62/77頁 |
| 文件大?。?/td> | 901K |
| 代理商： | PM5352-B1 |
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PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
58
Register 0x400: Master Test
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Reserved
PMCATST
PMCTST
DBCTRL
IOTST
HIZDATA
HIZIO
X
X
X
X
0
0
0
0
W
W
W
W
R/W
W
R/W
This register is used to enable S/UNI-STAR test features. All bits, except
PMCTST, PMCATST and BYPASS are reset to zero by a reset of the
S/UNI-STAR using either the RSTB input or the Master Reset register.
PMCTST and BYPASS are reset when CSB is logic one. PMCATST is
reset when both CSB is high and RSTB is low. PMCTST, PMCATST and
BYPASS can also be reset by writing a logic zero to the corresponding
register bit.
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the
S/UNI-STAR . While the HIZIO bit is a logic one, all output pins of the
S/UNI-STAR except the data bus and output TDO are held tri-state.
The microprocessor interface is still active. While the HIZDATA bit is a
logic one, the data bus is also held in a high-impedance state which
inhibits microprocessor read cycles. The HIZDATA bit is overridden by
the DBCTRL bit.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the
test registers and control the test mode in each TSB block in the
S/UNI-STAR for board level testing. When IOTST is a logic one, all
blocks are held in test mode and the microprocessor may write to a
block's test mode 0 registers to manipulate the outputs of the block
and consequentially the device outputs (refer to the "Test Mode 0
Details" in the "Test Features" section).
This Material Copyrighted by Its Respective Manufacturer
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