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PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
66
4.3.4
CH_RAM Interface Signals
Table 11. CH_ RAM Interface Signals (58 Pins)
Signal Name
Ball
Type
Drive/
Input Level
Slew
Rate
Description
CH_RAM_ADD(17:0)
R5, R3, R4, N1, N2, N3,
M2, N4, P3, K2, L2, P4,
M4, M3, M5, P5, N5, H2
Out
5 ma
Mod
CH_ RAM Address Bits 17 to 0
are part of the 18-bit SRAM
address bus.
CH_RAM_DATA(31:0)
AB5, AC3, AB2, AC2,
AA4, AB3, AB4, Y5, Y3,
AA5, Y4, Y2, AA3, AA2,
W3, V5, U5, W4, V3, U4,
W2, V2, V4, U3, U2, T2,
U1, R2, T3, T4, T5, P2
Bidir
5 ma/CMOS
Mod
CH_RAM Data Bits 31 to 0
are
part of the 32-bit SRAM data
bus.
CH_RAM_PARITY0
W5
Bidir
5 ma/CMOS
Mod
Odd parity bit for
CH_RAM_DATA(15:0).
CH_RAM_PARITY1
AD3
Bidir
5 ma/CMOS
Mod
Odd parity bit for
CH_RAM_DATA(31:16).
CH_RAM_CLK
K3
Out
8 ma
Fast
CH_RAM Clock
provides the
clock to the CH_RAM.This
signal should be terminated
with a series resistor before
connecting to the RAM mod-
ules
CH_RAM_ADD17N
K5
Out
5 ma
Mod
CH_RAM Not Address Bit 17
reverses bit 17 of
CH_RAM_ADD(17:0).
/CH_RAM_OE
J2
Out
8 ma
Fast
CH_RAM Output Enable
is an
active low signal that enables
the SRAM to drive the
CH_RAM_DATA(31:0),
CH_RAM_PARITY0, and
CH_RAM_PARITY1.This
signal should be terminated
with a series resistor before
connecting to the RAM mod-
ules
/CH_RAM_WE0
J3
Out
5 ma
Mod
CH_RAM Write Enable 0
is an
active low signal that strobes
CH_RAM_DATA(15:0) and
CH_RAM_PARITY0 into an
external SRAM.
/CH_RAM_WE1
L3
Out
5 ma
Mod
CH_RAM Write Enable 1
is an
active low signal that strobes
CH_RAM_DATA(31:16) and
CH_RAM_PARITY1 into an
external SRAM.