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PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
67
4.3.5
AL_RAM Interface Signals
Table 12. Address Lookup RAM Interface Signals (42 Pins)
/CH_RAM_ADSC
L4
Out
5 ma
Mod
CH_RAM Synchronous
Address
Status Controller
is an
active low signal that causes
new addresses to be registered
within the external SSRAM.
Signal Name
Ball
Type
Drive/
Input Level
Slew
Rate
Description
ALRAM_ADD(18:0)
AE8, AG7, AG6, AH5,
AF7, AF6, AH4, AG5,
AG4, AE7, AE6, AF5,
AG3, AE4, AC5, AF4,
AF3, AG2, AE3
Out
5 ma
Mod
AL RAM Address Bits 18 to 0
are
part of the 19-bit SRAM address
bus.
ALRAM_DATA(16:0)
AG11, AH9, AG9,
AH10, AF11, AE10,
AG10, AE11, AF9,
AG8, AF10, AJ6, AH8,
AF8, AE9, AH7, AH6
Bidir
5 ma/CMOS
Mod
AL RAM Data Bits 15 to 0
are part
of the 16-bit SRAM data bus.
Bit 16 is for parity.
ALRAM_CLK
AD1
Out
8 ma
Fast
AL RAM Clock
provides the clock
to the ALRAM. This signal should
be terminated with a series resistor
before connecting to the RAM
modules
ALRAMADD17N
AD4
Out
5 ma
Mod
AL RAM Not Address 17
reverses
bit 17 of ALRAM_ADD(18:0).
ALRAMADD18N
AD2
Out
5 ma
Mod
AL RAM Not Address 18
reverses
bit 18 of ALRAM_ADD(18:0).
/ALRAM_OE
AE2
Out
8 ma
Fast
AL RAM Output Enable
is an
active low signal that enables the
SRAM to drive
AL_RAM_DATA(16:0).This sig-
nal should be terminated with a
series resistor before connecting to
the RAM modules
/ALRAM_WE
AF2
Out
5 ma
Mod
AL RAM Write Enable
is an active
low signal that strobes data into an
external SRAM.
/ALRAM_ADSC
AC4
Out
5 ma
Mod
AL RAM Synchronous Address
Status Controller
is an active low
signal that causes new addresses
to be registered within the external
SSRAM.
Table 11. CH_ RAM Interface Signals (58 Pins) (Continued)
Signal Name
Ball
Type
Drive/
Input Level
Slew
Rate
Description