參數(shù)資料
型號(hào)： PowerPC 750CX
廠商： IBM Microeletronics
英文描述： 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精簡(jiǎn)指令集微處理器)
中文描述： 32位精簡(jiǎn)指令集計(jì)算機(jī)（RISC）微處理器（32位精簡(jiǎn)指令集微處理器）
文件頁(yè)數(shù)： 30/44頁(yè)
文件大小： 562K
代理商： POWERPC 750CX
PowerPC 750CX RISC Microprocessor Datasheet
Page 30
Version 1.1
November 13, 2000
Table 14: PowerPC 750CX Microprocessor PLL Configuration
PLL_CFG
(0:3)
Processor to
Bus Frequency
Ratio
(r)
Frequency Range Supported by VCO having an example range of
VCO
MIN
= 600 to VCO
MAX
= 1200MHz
6
SYSCLK
Core
bin
dec
Min
Max
Min
Max
0000
0
2.5x
120
133
5
300
333
0001
1
7.5x
40
80
300
600
6
0010
2
7x
43
86
0011
3
PLL Bypass
3
N/A
N/A
N/A
N/A
0100
4
2x
Note 1
Note 1
Note 1
Note 1
0101
5
6.5x
46
93
300
600
6
0110
6
10x
31
2
60
310
600
6
0111
7
4.5x
66
133
300
600
6
1000
8
3x
100
133
5
1001
9
5.5x
55
109
1010
10
4x
75
150
1011
11
5x
40
120
1100
12
8x
37
75
1101
13
6x
50
100
1110
14
3.5x
85
172
1111
15
Off
4
N/A
N/A
Off
Off
Note:
1. The 2X Processor to Bus Ratio is currently not supported.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see section “Clock AC Specifications” on page 13 for
valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for
1:1 mode operation. This mode is intended for factory use only.
Note:
The AC timing specifications given in the document do not apply
in PLL-bypass mode.
4. In Clock - off mode, no clocking occurs inside the PowerPC 750CX regardless of the SYSCLK input.
5. The SYSCLK limit is 133MHz, as specified in Table 6 on page 15. Applications requiring SYSCLK over 133MHz will be investigated by
application conditions.
6. VCO
is specified in this table by the maximum core processor speed. The VCO maximum of 1200MHz reflects a processor core
speed of 600MHz, which is not currently supported.
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