PowerPC 750CX RISC Microprocessor Datasheet
Page 38
Version 1.1
November 13, 2000
7.9
Operational and Design Considerations
7.9.1 Level Protection
A level protection feature is included in the PowerPC 750CX RISC Microprocessor in releases DD2.0 and later. The
level protection feature is available only in the 1.8V bus mode. This feature prevents ambiguous floating reference volt-
ages by pulling the respective signal line to the last valid or nearest valid state.
For example, if the I/O voltage level is closer to OV
DD
, the circuit pulls the I/O level to OV
DD
; if the I/O level is closer to
GND, the I/O level is pulled low. This self-latching circuitry “keeps” the floating inputs defined and avoids meta-stabil-
ity. In Table 16, these signals are defined as “keeper” in the "Level Protect" column.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of current
must be applied to the “keeper” node to overcome the level protection latch. This current is process dependent, but in no
case is the current required over 100
μ
A.
This feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce
costs.
7.9.2 64 or 32-Bit Data Bus Mode
Typical operation is considered to be in 64-bit Data Bus mode. Mode setting is determined by the state of the mode sig-
nal (QACK) at the transition of HRESET from its active to inactive state (low to high). If QACK is
low
when HRESET
transitions from active to inactive, 64-bit mode is selected. If QACK is
high
when HRESET transitions from active to
inactive, 32-bit mode is selected.
7.9.3 1.8V and 2.5V I/O Signal Support
Selection between 1.8V and 2.5V I/O is accomplished using the BVSEL pin. If BVSEL is set low then the 1.8V mode is
enabled. If BVSEL is set high, then the 2.5V mode is enabled.