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參數(shù)資料
| 型號(hào)： | PowerPC 750CX |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit Reduced Instruction Set Computer (RISC) Microprocessors(32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 32位精簡(jiǎn)指令集計(jì)算機(jī)（RISC）微處理器（32位精簡(jiǎn)指令集微處理器） |
| 文件頁數(shù)： | 31/44頁 |
| 文件大小： | 562K |
| 代理商： | POWERPC 750CX |
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PowerPC 750CX RISC Microprocessor Datasheet
November 13, 2000
Version 1.1
Page 31
7.2
PLL Power Supply Filtering
The AV
DD
power signal is provided on the PowerPC 750CX to provide power to the clock generation phase-locked loop.
To ensure stability of the internal clock, the power supplied to the AV
DD
input signal should be filtered using a circuit
similar to the one shown in Figure 15. The circuit should be placed as close as possible to the AV
DD
pin to ensure it filters
out as much noise as possible. The referenced ferrite bead, FB, shown in Figure 14 should supply an impedance of
approximately 30 ohms in the 100 MHz region.
7.3
Decoupling Recommendations
Due to the PowerPC 750CX’s feature large address and data buses, and high operating frequencies, the PowerPC 750CX
can generate transient power surges and high frequency noise in its power supply, especially while driving large capaci-
tive loads. This noise must be prevented from reaching other components in the PowerPC 750CX system, and the Pow-
erPC 750CX itself requires a clean, tightly regulated source of power.
Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low ESR
(effective series resistance) rating at each V
DD
and OV
DD
pin of the PowerPC 750CX. It is also recommended that these
decoupling capacitors receive their power from separate V
DD
, OV
DD
, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should range in value from 220pF to 10
μ
F to provide both high and low-frequency filtering, and should
be placed as close as possible to their associated V
DD
or OV
DD
pins. Suggested values for the V
DD
pins: 220pF (ceramic
X7R), 0.01
μ
F (ceramic X7R), and 0.1
μ
f (ceramic X7R). Suggested values for the OV
DD
pins: 0.01
μ
F (ceramic X7R),
0.1
μ
f (ceramic X7R), and 10
μ
F (tantalum). Only SMT (surface-mount technology) capacitors should be used to mini-
mize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V
DD
and OV
DD
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR
(equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the
power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors: 100
μ
F (AVX TPS tantalum) or 330
μ
F (AVX TPS tantalum).
7.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused
active low inputs should be tied to OV
DD
. Unused active high inputs should be connected to GND. All NC (no-connect)
signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, OV
DD
, and GND pins of the PowerPC 750CX.
Figure 15. PLL Power Supply Filter Circuit
V
DD
AV
DD
2
10
μ
F
0.1
μ
F
GND
FB
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