參數(shù)資料
型號: PPC5567MVR132
廠商: Freescale Semiconductor
文件頁數(shù): 40/68頁
文件大?。?/td> 0K
描述: MCU 32BIT POWERPC 416-PBGA
標(biāo)準(zhǔn)包裝: 200
系列: MPC55xx Qorivva
核心處理器: e200z6
芯體尺寸: 32-位
速度: 132MHz
連通性: CAN,EBI/EMI,以太網(wǎng),SCI,SPI
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 238
程序存儲器容量: 2MB(2M x 8)
程序存儲器類型: 閃存
RAM 容量: 80K x 8
電壓 - 電源 (Vcc/Vdd): 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 40x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 416-BBGA
包裝: 托盤
Electrical Characteristics
MPC5567 Microcontroller Data Sheet, Rev. 2
Freescale
45
3.13.9
eQADC SSI Timing
Figure 27. EQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics
Spec
Rating
Symbol
Minimum
Typical
Maximum
Unit
2
FCK period (tFCK = 1 fFCK) 1, 2
1 SS timing specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency
varies depending on track delays, master pad delays, and slave pad delays.
2 FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number.
tFCK
2—
17
tSYS_CLK
3
Clock (FCK) high time
tFCKHT
tSYS_CLK 6.5
9
(tSYS_CLK 6.5)
ns
4
Clock (FCK) low time
tFCKLT
tSYS_CLK 6.5
8
(tSYS_CLK 6.5)
ns
5
SDS lead / lag time
tSDS_LL
–7.5
+7.5
ns
6
SDO lead / lag time
tSDO_LL
–7.5
+7.5
ns
7
EQADC data setup time (inputs)
tEQ_SU
22
ns
8
EQADC data hold time (inputs)
tEQ_HO
1—
ns
1st (MSB)
2nd
25th
26th
1st (MSB) 2nd
25th
26th
8
7
5
6
4
5
4
2
3
FCK
SDS
SDO
External device data sample at
SDI
EQADC data sample at
FCK falling-edge
FCK rising-edge
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