參數(shù)資料
型號: PPC5567MVR132
廠商: Freescale Semiconductor
文件頁數(shù): 41/68頁
文件大?。?/td> 0K
描述: MCU 32BIT POWERPC 416-PBGA
標準包裝: 200
系列: MPC55xx Qorivva
核心處理器: e200z6
芯體尺寸: 32-位
速度: 132MHz
連通性: CAN,EBI/EMI,以太網(wǎng),SCI,SPI
外圍設備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 238
程序存儲器容量: 2MB(2M x 8)
程序存儲器類型: 閃存
RAM 容量: 80K x 8
電壓 - 電源 (Vcc/Vdd): 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 40x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 416-BBGA
包裝: 托盤
MPC5567 Microcontroller Data Sheet, Rev. 2
Electrical Characteristics
Freescale Semiconductor
46
3.14
Fast Ethernet AC Timing Specifications
Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic
(TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC
signals are independent of the system clock frequency (part speed designation).
3.14.1
MII FEC Receive Signal Timing
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK
The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent.
There is no minimum frequency requirement. The processor clock frequency must exceed four times the
FEC_RX_CLK frequency.
Table 28 lists MII FEC receive channel timings.
Figure 28 shows MII FEC receive signal timings listed in Table 28.
Figure 28. MII FEC Receive Signal Timing Diagram
Table 28. MII FEC Receive Signal Timing
Spec
Characteristic
Min.
Max
Unit
1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
ns
2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
ns
3
FEC_RX_CLK pulse-width high
35%
65%
FEC_RX_CLK period
4
FEC_RX_CLK pulse-width low
35%
65%
FEC_RX_CLK period
1
2
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
3
4
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