Table 5 ESD Characteristics: Added (Elec" />
參數(shù)資料
型號(hào)： PPC5567MVR132
廠商： Freescale Semiconductor
文件頁數(shù)： 58/68頁
文件大?。?/td> 0K
描述： MCU 32BIT POWERPC 416-PBGA
標(biāo)準(zhǔn)包裝： 200
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 238
程序存儲(chǔ)器容量： 2MB（2M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 80K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 416-BBGA
包裝： 托盤
Revision History for the MPC5567 Data Sheet
MPC5567 Microcontroller Data Sheet, Rev. 2
Freescale
61
Table 5 ESD Characteristics: Added (Electromagnetic Static Discharge) in the table title.
Table 6, VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies
fall outside the operating conditions and until the internal POR asserts.
Subscript all symbol names that appear after the first underscore character.
Removed ‘Tj ‘ after ‘150 C’ in the last line, second column: Characteristic.
Reformatted column layout.
Added footnote 1 to specs 1, 2, and 3 that reads: On power up, assert RESET before VPOR15, VPOR33, and VPOR5
negate (internal POR). RESET must remain asserted until the power supplies are within the operating conditions
as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies
fall outside the operating conditions and until the internal POR asserts.
Added to Spec 2:
3.3 V (VDDSYN) POR negated (ramp down)
Min 0.0
Max 0.30
V
3.3 V (VDDSYN) POR asserted (ramp up)
Min 0.0
Max 0.30
V
Spec 3: Added new footnote 3 for both lines: ‘It is possible to reach the current limit during ramp up--do not treat
this event as a short circuit current.’
Spec 5: Changed old Footnote 1 (now footnote 3): ‘User must be able to supply full operating current for the 1.5V
supply when the 3.3V supply reaches this range.” to ‘Supply full operating current for the 1.5 V supply when the
3.3 V supply reaches this range.”
Specs 7 and 10: added ‘a(chǎn)t Tj ‘ at the end of the first line in the second column: Characteristic.
Spec 10:
Changed the minimum values to: –40 C = 40; 25 C = 45; 150 C = 55.
Added old footnote 5 as new footnote 7.
Added cross-reference to footnote 6: ‘IVRCCTL is measured at the following conditions: VDD = 1.35 V,
VRC33 = 3.1 V, VVRCCTL = 2.2 V.’ Changed ‘(@ VDD = 1.35 V, fsys = fMAX)‘ to ‘(@ fsys = fMAX).
Added a new footnote 8, ‘Refer to Table 1 for the maximum operating frequency.’
Rewrote old footnote 7(new footnote 10) to: Represents the worst-case external transistor BETA. It is
measured on a per part basis and calculated as (IDD IVRCCTL).
Added new footnote 2 to both lines in Spec 3: “ VIL_S (Table 9, Spec 15) is guaranteed to scale with VDDEH6 down
to VPOR5.
Rewrote footnote 7 to read: Represents the worst-case external transistor BETA. It is measured on a per-part
basis and calculated as (IDD IVRCCTL).
Deleted old footnote 8: ‘Preliminary value. Final specification pending characterization.’
Table 7 Power Sequence Pin Status for Fast Pads
Changed title to Pin Status for Fast Pads During the Power Sequence
Changed preceding paragraph
From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive
current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting
POR, the pads are in a high impedance state (Hi-Z).
To: There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies
are powered.
Deleted the ‘Comment’ column.
Added to row 2, column 3, ‘Low’
Added row 3:’ VDDE, Low, Low, Asserted, High’ and row 5: VDDE, VDD33, VDD, Asserted, Hi-Z.
Added a POR column after the VDD column; all column entries are ‘Asserted’ except row 6: VDDE, VDD33, VDD,
negated, Functional.
Table 35. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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