Table 22 Bus Operation Timing: External Bu" />
參數(shù)資料
型號(hào)： PPC5567MVR132
廠商： Freescale Semiconductor
文件頁數(shù)： 62/68頁
文件大?。?/td> 0K
描述： MCU 32BIT POWERPC 416-PBGA
標(biāo)準(zhǔn)包裝： 200
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 238
程序存儲(chǔ)器容量： 2MB（2M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 80K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 416-BBGA
包裝： 托盤
Revision History for the MPC5567 Data Sheet
MPC5567 Microcontroller Data Sheet, Rev. 2
Freescale
65
Table 22 Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts
allow for 132 MHz system clock + 2% FM.
Spec 1: Changed the values in Min. columns: 40 MHz from 25 to 24.4; 56 MHz from 17.9 to 17.5, and the
66 MHz from 15.2 to 14.9.
Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
Specs 5, and 6: Deleted the BG, BR, and TSIZ[0:1] signals for arbitration. Added the following calibration signals:
CAL_ADDR[10:30], CAL_CS[0, 2:3], CAL_DATA[0:15], CAL_OE, CAL_RD_WR, CAL_TS, CAL_WE/BE[0:1].
Specs 7 and 8: Deleted the BG, BR, and TSIZ[0:1] signals for arbitration. Added the following calibration signals:
CAL_ADDR[10:30], CAL_DATA[0:15], CAL_RD_WR, and CAL_TS.
Added a footnote each for the DATA[0:31], TEA, and WE/BE[0:3] signals in the table: Due to pin limitations, the
DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package.
Table 23 External Interrupt Timing:
Footnote 1: Deleted ‘FSYS = 132 MHz.’,‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V.’ and
‘ and CL = 200 pF with SRC = 0b11.’
Deleted second figure after table ‘External Interrupt Setup Timing.’
Table 24 eTPU Timing
Footnote 1: Deleted ‘FSYS = 132 MHz.’, ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6’ and
‘ and CL = 200 pF with SRC = 0b11.’
Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Table 25 eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1: Deleted ‘FSYS = 132 MHz’, ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and
‘ and CL = 200 pF with SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 17 Added eMIOS Timing figure.
Table 26 DSPI Timing:
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts allow for 132 MHz system clock +
2% FM.
Spec1:SCK Cycle Time: changes to values: 80 MHz, min = 24.4, max 2.9; 112 MHz, min = 17.5, max = 2.1;
132 MHz, min = 14.8, max = 1.8.
Footnote 1: Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC =
0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew
rate.’ Deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 35. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
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