參數(shù)資料
型號： PSD813F4
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 42/130頁
文件大?。?/td> 650K
代理商： PSD813F4
PSD813F Famly
Prelimnary
38
The
PSD813F
Functional
Blocks
(cont.)
Each of the two PLDs has unique characteristics suited for its applications They are
described in the following sections.
9.2.1 Decode PLD(DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external
components. The DPLD can generate the following decode signals:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the optional EEPROM or Flash Boot memory
(three product terms each)
1 internal SRAM select signal (two product terms)
1 internal CSIOP (PSD configuration register) select signal
1 JTAG select signal (enables JTAG on Port C)
2 internal peripheral select signals (peripheral I/O mode).
9.2.2 Complex PLD(CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters
and shift registers, system mailboxes, handshaking protocols, state machines, and random
logic. The CPLD can also be used to generate 3 external chip selects, routed to Port D.
Although external chip selects can be produced by any Output Micro
Cell, these three
external chip selects on Port D do not consume any Output Micro
Cells.
As shown in Figure 12, the CPLD has the following blocks:
24 Input Micro
Cells (IMCs)
16 Output Micro
Cells (OMCs)
Micro
Cell Allocator
Product Term Allocator
AND array capable of generating up to 137 product terms
Four I/O ports.
Each of the blocks are described in the subsections that follow.
The Input and Output Micro
Cells are connected to the PSD813F internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output Micro
Cells or read data from both the Input and Output Micro
Cells.
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND logic array as required in most standard PLD macrocell
architectures.
相關PDF資料
PDF描述
PSD813F Flash In-System-Programmable Microcontroller Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
PSD813FH(中文) Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
PSD813FN(中文) Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器)
PSD813FN Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器)
PSD813FH Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
相關代理商/技術參數(shù)
參數(shù)描述
PSD813F4-15J 制造商:WSI 功能描述:
PSD813F4-15JI 制造商:WSI 功能描述:
PSD813F4A-90J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2A-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4A-90M 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2A-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4VA-15J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2VA-15J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
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