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參數(shù)資料
| 型號： | PSD813FN |
| 英文描述： | Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 1/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FN |
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1
Introduction
Prelimnary
Programmable Peripheral
PSD813FN/FH
Field-Programmable Microcontroller Peripherals
with Flash Memory and Embedded Micro
Cells
TM
Key Features
The PSD813FH and PSD813FN devices are field-programmable microcontroller (MCU)
peripherals with Flash memory. These multi-chip modules (MCM) are the first two members
of a complete family of in-system-programmable (ISP) peripherals from WSI that enhance
any embedded microcontroller design. These devices will interface easily with most popular
MCUs and enable a simple two-chip solution that addresses virtually all of the MCUs
external needs. Major features provided by the PSD813FH/FN are large Flash memory,
concurrent OTP boot memory, battery backed SRAM, programmable I/O, programmable
logic, address space expansion, power management, code security, and small package
size.
A two-chip solution consisting of an MCU and a PSD813FN/FH reduces design and
manufacturing cost, reduces board space, lowers power consumption, and shortens
time-to-market while increasing design flexibility. In addition, in-system features such as
concurrent Flash read and write capability, dynamically reconfigurable I/O ports,
and low power management increases system performance and manufacturing flexibility.
New innovative
“microcontroller-macrocells”
, called Micro
Cells
TM
, bring inexpensive
programmable logic to MCU-based embedded system designs. Because the Micro
Cells
are directly connected to the MCU address/data bus, their programmable logic is
tightly coupled to the MCU software with no hardware overhead. The MCU’s ability to
communicate directly with the Micro
Cells at the flip-flop level makes PSD813FN/FH
devices ideal for popular functions such as counters, serial channels, and mailboxes. When
compared to industry standard CPLD implementation, this architecture can save 25% to
50% of the CPLD product term and macrocell resources.
The PSD813FN/FH devices are the first of WSI’s Flash PSD8XXF product family. Starting
with the PSD813FN/FH, a pin-for-pin upgrade path exists for future lower cost monolithic
PSD8XXF devices that will incorporate expanded Flash-based programmable logic, Flash
and EEPROM memory types, larger SRAM, and serial ISP using the industry standard
JTAG protocol.
J
MCM 5-volt only Flash Programmable Peripheral for Microcontroller-based
Applications
J
Solves Problems of In-System Flash Erase and Programming
– Concurrently Operating Main Memory and Boot Memory
– Resolves Microcontroller Decoding Issues During Flash Update
J
Two separate non-volatile memory arrays.
Both 1 Mbit (128 Kbytes) of Flash memory and 256 Kbits (32 Kbytes) of Separate OTP
Boot EPROM memory are available. The Boot memory allows continuous operation
of the MCU while the Flash memory is being written or erased. The Flash memory is
divided into eight 16 Kbyte sectors that can be mapped to different address spaces.
Access time is 150 ns which includes address latching and DPLD decoding.
J
Embedded On-Chip Erase and Program Algorithms for the Flash Memory.
Automatically accommodates on-chip events for writing and erasing the Flash memory.
The Flash memory is byte-programmable and can be erased sector by sector or by
entire chip. The embedded algorithms indicate completion of program or erase cycles
by using two popular methods: data polling or bit toggling. PSD813FN/FH algorithms
are compatible with the standard JEDEC single-power-supply Flash command set.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD813FH | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| PSD82 | Three Phase Rectifier Bridges |
| PSD834F2V | Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.) |
| PSD834F2 | Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的閃速ISP外圍) |
| PSD835G2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲器可編程外設(shè)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813FN-15J | 制造商:WSI 功能描述: |
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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