
PXB 4330
Functional Description
Data Sheet
3-37
09.99
3
Functional Description
3.1
The ABM Core
Figure 3-1
shows the block diagram of an ATM Buffer Manager (ABM) Core. Cells with
up to 687 Mbit/s (with 52 MHz SYSCLK) are assigned to Schedulers and queues within
the Cell Acceptance block. As it enters, each cell is checked to verify that it would not
exceed the respective thresholds which are provided for queues, schedulers, QoS class-
es (traffic classes), as well as the total buffer capacity. Once accepted, a cell cannot be
lost, but will appear at the output after some time (exception: queue has been disabled
while cells are stored).
The optional Peak Rate Limiter is provided for the shaping of individual queues.
The demultiplexer forwards the cells to the respective Scheduler. The Scheduler sorts
them into queues and schedules them for retransmission according to the programmed
configuration. The Scheduler is the key queuing element of the ABM. The behavior of
the Scheduler is described below. The output multiplexer combines the cell streams for
all Schedulers. Their output rates must be programmed such that the sum rate does not
exceed the total output bandwidth.
Figure 3-1
Block Diagram of one ABM Core
ABM Core
Cell
Acceptance
Thresholds
(Traffic Classes)
Cell
Input
scheduler block 1
d
e
m
u
x
out
in
global real time bypass
scheduler block 48
Legend:
Port with PCR, SCR
priority mux
cyclic mux
weighted fair queuing mux
queue
W
F
Q
real time bypass
VBR
ABR
UBR+
scheduler block i
UBR
W
F
Q
CBR, VBR-rt