
PXB 4330
Register Descriptions
Data Sheet
6-89
09.99
Internal Table 1: LCI Table Transfer Registers LCI0, LCI1
These registers are used to access the internal Local Connection Identifier (LCI) table
containing 8192 entries.
Table 6-3
shows an overview of the registers involved.
LCI0 and LCI1 are the transfer registers for one 32-bit LCI table entry. The LCI value
representing the table entry which needs to be Read or modified must be written to the
Word Address Register (
WAR
). The dedicated LCI table entry is Read into the LCI1/LCI0
Registers or modified by the LCI1/LCI0 Register values with a Read-Modify-Write
mechanism. The associated Mask Registers MASK0 and MASK1 allow a bit-by-bit
selection between Read (1) and Write (0) operation. In case of Read operation, the
dedicated LCI1/LCI0 register bit will be overwritten by the respective LCI table entry bit
value. In case of Write operation, the dedicated LCI1/LCI0 register bit will modify the
respective LCI table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (
MAR
).
The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to
select the LCI table bit field MAR(4:0) must be set to 0. Bit 5 of the MAR starts the
transfer and is automatically cleared after execution of the Read-Modify-Write process.
Table 6-4
WAR Register Mapping for LCI Table Access
Table 6-3
31
Registers for LCI Table Access
0
LCI RAM entry
0
RAM select:
15
15
0
15
0
LCI1
LCI0
MAR=00
H
LCI select:
15
0
15
0
15
0
MASK1
MASK0
WAR (0..8191
D
)
Bit
15
14
13
12
11
10
9
8
Unused(2:0)
LCISel(12:8)
Bit
7
6
5
4
LCISel(7:0)
3
2
1
0
LCISel(12:0)
Selects an LCI entry within the range (0..8191).