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參數(shù)資料
| 型號： | QL901M-6PS680I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | QuickMIPS ESP Family |
| 中文描述： | QuickMIPS ESP家庭 |
| 文件頁數(shù)： | 12/37頁 |
| 文件大?。?/td> | 432K |
| 代理商： | QL901M-6PS680I |
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Figure 11: RAM Cell Synchronous Write Timing
Table 9: RAM Cell Synchronous & Asynchronous Read Timing
Symbol
Parameter
Propagation
delay (ns)
RAM Cell Synchronous Read Timing
tSRA
RA setup time to RCLK: the amount of time the READ ADDRESS must
be stable before the active edge of the READ CLOCK
0.686
tHRA
RA hold time to RCLK: the amount of time the READ ADDRESS must
be stable after the active edge of the READ CLOCK
0
tSRE
RE setup time to WCLK: the amount of time the READ ENABLE must be
stable before the active edge of the READ CLOCK
0.243
tHRE
RE hold time to WCLK: the amount of time the READ ENABLE must be
stable after the active edge of the READ CLOCK
0
tRCRD
RCLK to RD: the amount of time between the active READ CLOCK edge
and the time when the data is available at RD
4.38
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: amount of time between when the READ ADDRESS is input
and when the DATA is output
2.06
tSWA
tSWD
tSWE
tHWA
tHWD
tHWE
tWCRD
old data
new data
WCLK
WA
WD
WE
RD
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