參數(shù)資料
型號(hào)： QL901M-6PS680I
廠商： Electronic Theatre Controls, Inc.
英文描述： QuickMIPS ESP Family
中文描述： QuickMIPS ESP家庭
文件頁(yè)數(shù)： 3/37頁(yè)
文件大?。?/td> 432K
代理商： QL901M-6PS680I
QL901M QuickMIPS Data Sheet Rev B
3
Design Tools Platform Support
QuickWorks, the complete product suite, supports Windows 95/98/NT/2000. It includes SpDE
(layout including place & route, timing analysis, and back-annotation), Synplify-Lite (synthesis), Turbo
Writer (HDL-enhanced text editor), etc.
QuickTool supports Solaris. It has only the layout software (SpDE).
QuickMIPS simulation is enabled through either:
a SmartModel (VMC-generated model, encrypted RTL, relatively slow). This option supports both
Verilog and VHDL.
SaiLAhead co-verification platform from Saivision (very fast C model). This option only supports
Verilog (no VHDL) at this time.
SaiLAhead Platform
The “SaiLAhead for QuickMIPS” co-verification platform is tailored for QuickMIPS devices. It enables
simulation of user-defined logic functions that are to be implemented in the QuickMIPS programmable
fabric with the rest of the QuickMIPS fixed system logic functions, which verifies overall QuickMIPS
functionality. Simultaneously, the SaiLAhead platform has a powerful, feature-rich debugger, which
enables QuickMIPS users to develop and debug their application code (C and MIPS assembly). The
SaiLAhead platform accelerates the speed of simulation of the QuickMIPS device in a simulator such as
NC-Verilog by using C models for various fixed system logic functions in the QuickMIPS device. This
entire QuickMIPS design. Please refer to
http://www.saivision.com
for more information on the
SaiLAhead platform.
Table 2: Design Tools Platform Support
Solaris
Windows NT
Windows 2000
Linux
Synthesis
Synplify-Lite
X
(in QuickWorks)
X
(in QuickWorks)
Layout
SpDE
X
(in QuickTool)
X
(in QuickWorks)
X
(in QuickWorks)
Simulation
SmartModel
ModelSim/VCS
X
X
Verilog XL/NC
X
SaiLAhead
ModelSim
X
X
X
Verilog XL/NC
X
X
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