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參數(shù)資料
| 型號： | QL901M-6PS680I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | QuickMIPS ESP Family |
| 中文描述： | QuickMIPS ESP家庭 |
| 文件頁數(shù)： | 30/37頁 |
| 文件大?。?/td> | 432K |
| 代理商： | QL901M-6PS680I |
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M1_TXCLK/M2_TXCLK
I
Ethernet Transmit Clock. TXCLK is a continuous clock that provides a timing reference for the transfer
of the TXEN and TXD signals from the MAC110 core to the Ethernet PHY Controller. The Ethernet PHY
Controller chip sources TXCLK. The operating frequency of TXCLK is 25 MHz when operating at
100 Mbps and 2.5 MHz when operating at 10 Mbps.
M1_TXD[3:0]/M2_TXD[3:0]
O
Ethernet Transmit Data. The QuickMIPS MAC110 core drives TXD[3:0]. TXD[3:0] transition
synchronously with respect to TXCLK. For each TXCLK period in which TXEN is asserted, TXD[3:0]
have the data to be accepted by the Ethernet PHY Controller chip. TXD0 is the least-significant bit.
While TXEN is deasserted, ignore the data presented on TXD[3:0].
M1_TXEN/M2_TXEN
O
Ethernet Transmit Enable. A high assertion on TXEN indicates that the MAC110 core is presenting
nibbles on the MII for transmission. The QuickMIPS MAC110 core asserts TXEN with the first nibble of
the preamble and holds TXEN asserted while all nibbles to be transmitted are presented to the MII.
TXEN is deasserted low prior to the first TXCLK following the final nibble of the frame. TXEN is
transitions synchronously with respect to TXCLK.
Memory Controller Interface Signals
BLS_n[3:0]
O
Byte Enables. These signals determine the validity of the bytes on the DATA bus.
CS_n[7:0]
O
Chip Selects. These signals are the active-low chip selects for the SRAM.
ADDR[23:0]
O
Memory Address. This 24-bit address contains the memory address.
DATA[31:0]
I/O
Memory Data. This 32-bit bus contains the memory data.
OEN_n
O
SRAM Output Enable. OEN_n is the active-low output enable to the external SRAM.
SD_CAS_n
O
SDRAM Column Address Strobe. SD_CAS_n is the active-low column address strobe for the external
SDRAM.
SD_CKE[3:0]
O
SDRAM Output Clock Enables. SD_CKE[3:0] determine whether the next clock is valid or not.
SD_CLKIN
I
SDRAM Input Clock. SD_CLKIN is the external SDRAM clock.
SD_CLKOUT
O
SDRAM Output Clock. SD_CLKOUT is the clock from the QuickMIPS chip to the external SDRAMs.
SD_CS_n[3:0]
O
SDRAM Output Chip Select. SD_CS_n[3:0] are the active-low chip selects for the external SDRAMs.
SD_DQM[3:0]
O
SDRAM Data Mask. SD_DQM[3:0] are the data masks for DATA[31:0]
SD_RAS_n
O
SDRAM Row Address Strobe. SD_RAS_n is the active-low row address strobe for the external
SDRAM.
SD_WE_n
O
SDRAM Write Enable. SD_WE_n is the active-low write enable to the SDRAMs.
WEN_n
O
SRAM Transfer Direction. WEN_n indicates whether transactions between the QuickMIPS chip and the
external SRAM are reads (WEN_n is high) or writes (WEN_n is low).
UART Interface Signals
U1_CTS_n
I
UART1 Clear To Send. A low on this signal indicates the external device is ready to transfer data.
U1_DCD_n
I
UART1 Data Carrier Detect. A low on this signal indicates the data carrier has been detected.
U1_DSR_n
I
UART1 Data Set Ready. A low on this signal indicates the modem or data set is ready to establish the
link to the QuickMIPS UART.
U1_DTR_n
O
UART1 Data Terminal Ready. The QuickMIPS chip asserts this output low to indicate it is ready to
establish the external communication link.
U1_RI_n
I
UART1 Ring Indicator. This input is an active-low ring indicator.
U1_RTS_n
O
UART1 Request To Send. The QuickMIPS chip asserts this signal low to inform the external device that
the UART is ready to send data.
U1_RXD_SIRIN
I
UART1 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the
UART or the IrDA block.
Table 27: Pin Descriptions (Continued)
Pin
I/O
Function
(Sheet 4 of 6)
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