Programmable Via-Link Fabric
Embedded memory configurable as RAM or FIFO
252 programmable I/Os
High-speed dynamically configurable ECUs enable hardware implementation of DSP functions with
3-bit instructions
Fabric I/O standard options: LVTLL, LVCMOS, PCI, GTL+, SSTL, and SSTL3
On-Chip Debug Blocks
On-chip instrumentation blocks for debug and trace capabilities
Configurable Logic Analysis Module (CLAM) blocks with IP in programmable fabric allow user to look
at selected signals from IP function in fabric
Development and Programming
Complete QuickLogic software suite of development tools enables rapid implementation of IP
functions for complete SOC solution
Complete chip simulation of user-defined programmable-logic IP functions with the processor,
caches, memory, and all hardwired functions on-chip
Synthesis of IP functions into the programmable fabric
Place-and-Route tool for efficient implementation of IP functions in the programmable fabric
Extensive timing analysis of IP functions with the rest of the chip to ensure full chip functionality
Programming and debug support of the entire chip through JTAG port
Integrated debug support for the MIPS 4Kc processor
MIPS Language and Debug tool support for the MIPS 4Kc processor from approved third party
MIPS vendors
ECU support for a variety of DSP algorithms and functions
QuickLogic library of standard IP functions for plug-and-play implementation of standard IP functions
in the programmable fabric for a complete SOC solution
QuickMIPS Reference Design Kit (RDK) provides a complete Board Support Package for
chip evaluation
Programming and debug support
Device-driver support for standard IP functions
Boot-up code and diagnostics
Table 1: Programmable Fabric Features
Maximum System Gates*
Logic Arrays
Columns x Rows
Logic Cells
Maximum
Flip-Flops
RAM Blocks** RAM Bits
ECU Blocks***
536,472
72x28
2,016
4,788
36
82,944
18
* 75K ASIC gates
** Possible Configurations:
128x18, 256x9, 512x4, or 1024x2
*** 8x8 Multiply,
16-bit carry-add