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參數(shù)資料
| 型號： | QL901M-6PS680I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | QuickMIPS ESP Family |
| 中文描述： | QuickMIPS ESP家庭 |
| 文件頁數(shù)： | 5/37頁 |
| 文件大?。?/td> | 432K |
| 代理商： | QL901M-6PS680I |
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QL901M QuickMIPS Data Sheet Rev B
5
The ECU block can be configured for eight arithmetic functions via an instruction as shown in
Table 4
.
The modes for the ECU block are dynamically reprogrammable through the Instruction Set Sequencer.
The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an
external software driven algorithm, or an internal state machine. This flexibility allows the designer to
reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock
cycle, such as adaptive filtering.
3.0 Design Flow
The QuickMIPS design flow, similar to ASIC design flow, is shown in
Figure 3
.
Figure 3: QuickMIPS Hardware/Software Co-Development Flow
Table 4: ECU Mode Select Criteria
Instruction Set
Operation
0
0
0
Multiply
0
0
1
Multiply - Add
0
1
0
Accumulate
0
1
1
Add
1
0
0
Multiply (registered)
1
0
1
Multiply - Add (registered)
1
1
0
Multiple - Accumulate
1
1
1
Add (registered)
MIPS Programming
System Configuration
Customer IP Design in FPGA
Assembler, Linker
Compiler,
Configuration
Global Register
Debugger
RTL
Synthesis
Place & Route
Timing Analysis
& Timing
Final Netlist
QuickIP Netlist
Timing Lib
Synthesis Lib
QuickIP Models
Full-System
with Timing
Functional Co-simulation
Chip Programming
EJTAG
Board-level
Support Package
Model
QuickMIPS
System
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