參數(shù)資料
型號(hào)： RTL8100CL-LF
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 27/73頁
文件大?。?/td> 652K
代理商： RTL8100CL-LF
RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
19
Track ID: JATR-1076-21 Rev. 1.06
5.16. Receive Configuration Register
(Offset 0044h-0047h, R/W)
This register is used to set the receive configuration for the RTL8100C(L). Receive properties such as
accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here.
Table 16. Receive Configuration Register
Symbol
Description
-
Reserved.
ERTH3, 2, 1, 0
Early Rx threshold bits.
These bits are used to select the Rx threshold multiplier of a whole
packet that has been transferred to the system buffer in early mode
whilst the frame protocol is under the RTL8100C(L)'s definition.
0000 = No early Rx threshold
0010 = 2/16
0100 = 4/16
0110 = 6/16
1000 = 8/16
1010 = 10/16
1100 = 12/16
1110 = 14/16
-
Reserved.
MulERINT
Multiple Early Interrupt select.
When this bit is set, any received packet invokes early interrupt
according to MULINT<MISR[11:0]> setting in early mode. When
this bit is reset, the packets of familiar protocols (IPX, IP, NDIS, etc)
invoke early interrupt according to RCR<ERTH[3:0]> setting in
early mode. The packets of unfamiliar protocols will invoke early
interrupt according to the setting of MULINT<MISR[11:0]>.
RER8
Receive Error 8 bytes.
1: The RTL8100C(L) accepts error packets with a length of 8~64
bytes.
0: The RTL8100C(L) accepts error packets with a length larger than
64 bytes. The power-on default is zero.
If AER or AR is set, the RER (Receive Error) will be set when the
RTL8100C(L) receives an error packet with a length larger than
8 bytes. RER8 is irrelevant in this situation.
Bit
31-28
27-24
R/W
-
R/W
0001 = 1/16
0011 = 3/16
0101 = 5/16
0111 = 7/16
1001 = 9/16
1011 = 11/16
1101 = 13/16
1111 = 15/16
23-18
17
-
R/W
16
R/W
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