RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
iii
Track ID: JATR-1076-21 Rev. 1.06
Table of Contents
1.
GENERAL DESCRIPTION...............................................................................................................1
2.
FEATURES..........................................................................................................................................2
3.
BLOCK DIAGRAM............................................................................................................................3
4.
PIN ASSIGNMENTS..........................................................................................................................4
4.1. RTL8100C (QFP) & RTL8100CL (LQFP).....................................................................................4
5.
PIN DESCRIPTION............................................................................................................................5
5.1. P
OWER
M
ANAGEMENT
/I
SOLATION
I
NTERFACE
................................................................................5
5.2. PCI I
NTERFACE
................................................................................................................................6
5.3. EPROM/EEPROM I
NTERFACE
/AUX .............................................................................................8
5.4. P
OWER
P
INS
.....................................................................................................................................8
5.5. LED I
NTERFACE
...............................................................................................................................8
5.6. A
TTACHMENT
U
NIT
I
NTERFACE
.......................................................................................................9
5.7. T
EST AND
O
THER
P
INS
.....................................................................................................................9
5.8. R
EGISTER
D
ESCRIPTIONS
................................................................................................................10
5.9. R
ECEIVE
S
TATUS
R
EGISTER IN
RX P
ACKET
H
EADER
.....................................................................12
5.10. T
RANSMIT
S
TATUS
R
EGISTER
(TSD0-3)(O
FFSET
0010
H
-001F
H
, R/W)........................................13
5.11. ERSR: E
ARLY
RX S
TATUS
R
EGISTER
(O
FFSET
0036
H
, R) ............................................................14
5.12. C
OMMAND
R
EGISTER
(O
FFSET
0037
H
, R/W).................................................................................15
5.13. I
NTERRUPT
M
ASK
R
EGISTER
(O
FFSET
003C
H
-003D
H
, R/W).........................................................15
5.14. I
NTERRUPT
S
TATUS
R
EGISTER
(O
FFSET
003E
H
-003F
H
, R/W).......................................................16
5.15. T
RANSMIT
C
ONFIGURATION
R
EGISTER
(O
FFSET
0040
H
-0043
H
, R/W)...........................................17
5.16. R
ECEIVE
C
ONFIGURATION
R
EGISTER
(O
FFSET
0044
H
-0047
H
, R/W).............................................19
5.17. 9346CR: 93C46 C
OMMAND
R
EGISTER
(O
FFSET
0050
H
, R/W).....................................................22
5.18. CONFIG 0: C
ONFIGURATION
R
EGISTER
0 (O
FFSET
0051
H
, R/W)................................................23
5.19. CONFIG 1: C
ONFIGURATION
R
EGISTER
1 (O
FFSET
0052
H
, R/W)................................................23
5.20. M
EDIA
S
TATUS
R
EGISTER
(O
FFSET
0058
H
, R/W)..........................................................................24
5.21. CONFIG 3: C
ONFIGURATION
R
EGISTER
3 (O
FFSET
0059
H
, R/W).................................................25
5.22. CONFIG 4: C
ONFIGURATION
R
EGISTER
4 (O
FFSET
005A
H
, R/W)................................................27
5.23. M
ULTIPLE
I
NTERRUPT
S
ELECT
R
EGISTER
(O
FFSET
005C
H
-005D
H
, R/W).....................................28