參數(shù)資料
型號(hào)： RTL8100CL-LF
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 單芯片快速以太網(wǎng)控制器電源管理
文件頁(yè)數(shù)： 43/73頁(yè)
文件大小： 652K
代理商： RTL8100CL-LF
RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
35
Track ID: JATR-1076-21 Rev. 1.06
5.37. EEPROM (93C46) Contents
The 93C46 is a 1 Kbit EEPROM. Although it is addressed by words, its contents are listed below by bytes
for convenience. The RTL8100C(L) performs a series of EEPROM read operations from the 93C46
addresses 00H to 31H.
It is suggested you obtain Realtek approval before changing the default settings of the EEPROM.
Table 37. EEPROM (93C46) Contents
Description
These 2 bytes contain the ID code word for the RTL8100C(L). The RTL8100C(L) will
load the contents of the EEPROM into the corresponding location if the ID word (8129h)
is right, otherwise, the RTL8100C(L) will not proceed with the EEPROM auto load
process.
Reserved. The RTL8100C(L) no longer supports auto load of Vender ID and Device
ID. The default values of VID and DID are hex 10EC and 8139, respectively.
PCI Subsystem Vendor ID.
PCI configuration space offset 2Ch-2Dh.
PCI Subsystem ID.
PCI configuration space offset 2Eh-2Fh.
PCI Minimum Grant Timer.
PCI configuration space offset 3Eh.
PCI Maximum Latency Timer.
PCI configuration space offset 3Fh.
Bits 7-6 map to bits 7-6 of the Media Status Register (MSR).
Bits 5, 4, 0 map to bits 13, 12, 8 of the Basic Mode Control Register (BMCR).
Bits 3-2 are reserved.
If the network speed is set to Auto-Detect mode (i.e. NWay mode), then Bit 1=0
means the local RTL8100C(L) supports flow control (IEEE 802.3x). In this case, Bit
10=1 in the Auto-negotiation Advertisement Register (offset 66h-67h).
If Bit 1=1 this means the local RTL8100C(L) does not support flow control. In this
case, Bit 10=0 in Auto-negotiation Advertisement. This is because some NWay
switching hubs randomly send flow control pause packets if the link partner supports
NWay flow control.
RTL8100C(L) Configuration register 3.
Operational register offset 59H.
After an auto load command or hardware reset, the RTL8100C(L) loads the Ethernet
ID to IDR0-IDR5 of the RTL8100C(L)’s I/O registers.
RTL8100C(L) Configuration register 0.
Operational registers offset 51h.
RTL8100C(L) Configuration register 1.
Operational registers offset 52h.
Power Management Capabilities.
PCI configuration space address 52h and 53h.
Reserved. Do not change this field without Realtek approval.
Power Management Control/Status.
PCI configuration space address 55h.
Reserved. Do not change this field without Realtek approval.
Bytes
00h
01h
Contents
29h
81h
02h-05h
-
06h-07h
SVID
08h-09h
SMID
0Ah
MNGNT
0Bh
MXLAT
0Ch
MSRBMCR
0Dh
CONFIG3
0Eh-13h
Ethernet ID
14h
CONFIG0
15h
CONFIG1
16h-17h
PMC
18h
PMCSR
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