參數(shù)資料
型號(hào)： RTL8100CL
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 21/73頁
文件大?。?/td> 652K
代理商： RTL8100CL
RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
13
Track ID: JATR-1076-21 Rev. 1.06
Bit
2
R/W
R
Symbol
CRC
Description
Cyclic Redundancy Check (CRC) Error.
When set, indicates that a CRC error occurred on the received
packet.
Frame Alignment Error.
When set, indicates that a frame alignment error occurred on this
received packet.
Receive OK.
When set, indicates that a good packet was received.
1
R
FAE
0
R
ROK
5.10. Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100C(L)
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected
when software writes to these bits. These registers are only permitted to be written via double-word access.
After a software reset, all bits except OWN bit are reset to 0.
Table 10. Transmit Status Register
Symbol
Description
CRS
Carrier Sense Lost.
This bit is set to 1 when the carrier is lost during transmission of a
packet.
TABT
Transmit Abort.
This bit is set to 1 if the transmission of a packet was aborted. This bit
is read only, writing to this bit is not affected.
OWC
Out of Window Collision.
This bit is set to 1 if the RTL8100C(L) encountered an ‘out of window’
collision during the transmission of a packet.
CDH
CD HeartBeat.
The NIC watches for a collision signal (i.e., CD Heartbeat signal)
during the first 6.4μs of the InterFrame Gap following a
transmission. This bit is set if the transceiver fails to send this signal.
This bit is cleared in 100Mbps mode.
NCC3-0
Number of Collision Count.
Indicates the number of collisions encountered during the
transmission of a packet.
-
Reserved.
ERTXTH5-0
Specifies the threshold level in the Tx FIFO to begin the
transmission. When the byte count of the data in the Tx FIFO reaches
this level, (or the FIFO contains at least one complete packet) the
RTL8100C(L) will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in units of 32 bytes.
This threshold must be prevented from exceeding 2k bytes.
Bit
31
R/W
R
30
R
29
R
28
R
27-24
R
23-22
21-16
-
R/W
Early Tx Threshold.
相關(guān)PDF資料
PDF描述
RTL8130 REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RTL8100C-LF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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RTL8100L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8101 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8101L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT
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