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參數(shù)資料
| 型號： | RTL8100CL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| 中文描述： | 單芯片快速以太網(wǎng)控制器電源管理 |
| 文件頁數(shù)： | 22/73頁 |
| 文件大?。?/td> | 652K |
| 代理商： | RTL8100CL |
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RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
14
Track ID: JATR-1076-21 Rev. 1.06
Bit
15
R/W
R
Symbol
TOK
Description
Transmit OK.
Set to 1 indicates that the transmission of a packet was completed
successfully and no transmit underrun has occurred.
Transmit FIFO Underrun.
Set to 1 if the Tx FIFO was exhausted during the transmission of a
packet. The RTL8100C(L) can re-transfer data if the Tx FIFO
underruns. That is, when TSD<TUN>=1, TSD<TOK>=0 and
ISR<TOK>=1 (or ISR<TER>=1).
OWN.
The RTL8100C(L) sets this bit to 1 when the Tx DMA operation of
this descriptor has completed. The driver must set this bit to 0 when
the Transmit Byte Count (bits 0-12) is written. The default value is 1.
Descriptor Size.
The total size in bytes of the data in this descriptor. If the packet
length is more than 1792 bytes (0700h), the Tx queue will be invalid,
i.e. the next descriptor will be written only after the OWN bit of that
long packet’s descriptor has been set.
14
R
TUN
13
R/W
OWN
12-0
R/W
SIZE
5.11. ERSR: Early RX Status Register (Offset 0036h, R)
Table 11. ERSR: Early RX Status Register
Symbol
Description
-
Reserved.
ERGood
Early Rx Good packet.
This bit is set whenever a packet is completely received and the
packet is good. Writing a 1 to this bit will clear it.
ERBad
Early Rx Bad packet.
This bit is set whenever a packet is completely received and the
packet is bad. Writing a 1 to this bit will clear it.
EROVW
Early Rx OverWrite.
This bit is set when the RTL8100C(L)’s local address pointer is equal
to CAPR. In Early Mode, this is different from buffer overflow. It
happens when the RTL8100C(L) detects an Rx error and wants to fill
another packet data from the beginning address of that error packet.
Writing a 1 to this bit will clear it.
EROK
Early Rx OK.
The power-on value is 0. It is set when the Rx byte count of the
arriving packet exceeds the Rx threshold. After the whole packet is
received, the RTL8100C(L) will set ROK or RER in ISR and clear
this bit simultaneously. Setting this bit will invoke an ROK interrupt.
Bit
7-4
3
R/W
-
R
2
R
1
R
0
R
相關PDF資料 |
PDF描述 |
|---|---|
| RTL8130 | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100 | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100B | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100BL | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100BLLQTP | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| RTL8100C-LF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100CL-LF | 制造商:Realtek Semiconductor 功能描述:RTL8100CL Series 3.6 V Fast Ethernet Controller with Power Management LQFP-128 |
| RTL8100L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8101L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC97 CONTROLLER WITH POWER MANAGEMENT |
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