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RTL8139C(L)
2002/01/10
Rev.1.4
10
6. Register Descriptions
The RTL8139C(L) provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset
0000h
R/W
R/W
Tag
IDR0
Description
ID Register 0:
The ID registers 0-5 are only permitted to read/write
by 4-byte access. Read access can be byte, word, or double word
access. The initial value is autoloaded from the EEPROM EthernetID
field.
ID Register 1
ID Register 2
ID Register 3
ID Register 4
ID Register 5
Reserved
Multicast Register 0:
The MAR registers 0-7 are only permitted to
read/write by 4-byte access. Read access can be byte, word, or double
word access. Driver is responsible for initializing these registers.
Multicast Register 1
Multicast Register 2
Multicast Register 3
Multicast Register 4
Multicast Register 5
Multicast Register 6
Multicast Register 7
Transmit Status of Descriptor 0
Transmit Status of Descriptor 1
Transmit Status of Descriptor 2
Transmit Status of Descriptor 3
Transmit Start Address of Descriptor0
Transmit Start Address of Descriptor1
Transmit Start Address of Descriptor2
Transmit Start Address of Descriptor3
Receive (Rx) Buffer Start Address
Early Receive (Rx) Byte Count Register
Early Rx Status Register
Command Register
Current Address of Packet Read
(The initial value is 0FFF0h)
Current Buffer Address:
The initial value is 0000h. It reflects total
received byte-count in the rx buffer.
Interrupt Mask Register
Interrupt Status Register
Transmit (Tx) Configuration Register
Receive (Rx) Configuration Register
Timer Count Register:
This register contains a 32-bit
general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin to count from zero.
Missed Packet Counter:
Indicates the number of packets discarded
due to rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
When any value is written, MPC will be reset also.
93C46 (93C56) Command Register
Configuration Register 0
Configuration Register 1
0001h
0002h
0003h
0004h
0005h
R/W
R/W
R/W
R/W
R/W
-
R/W
IDR1
IDR2
IDR3
IDR4
IDR5
-
MAR0
0006h-0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h-0013h
0014h-0017h
0018h-001Bh
001Ch-001Fh
0020h-0023h
0024h-0027h
0028h-002Bh
002Ch-002Fh
0030h-0033h
0034h-0035h
0036h
0037h
0038h-0039h
003Ah-003Bh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
TSD0
TSD1
TSD2
TSD3
TSAD0
TSAD1
TSAD2
TSAD3
RBSTART
ERBCR
ERSR
CR
CAPR
CBR
003Ch-003Dh
003Eh-003Fh
0040h-0043h
0044h-0047h
0048h-004Bh
R/W
R/W
R/W
R/W
R/W
IMR
ISR
TCR
RCR
TCTR
004Ch-004Fh
R/W
MPC
0050h
0051h
0052h
R/W
R/W
R/W
9346CR
CONFIG0
CONFIG1