參數(shù)資料
型號(hào)： RTL8139A
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱單芯片快速以太網(wǎng)控制器電源管理
文件頁(yè)數(shù)： 46/62頁(yè)
文件大小： 648K
代理商： RTL8139A
RTL8139C(L)
2002/01/10
Rev.1.4
46
9. Functional Description
9.1 Transmit Operation
The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the
entire packet has been transferred to the Tx buffer, the RTL8139C(L) is instructed to move the data from the Tx buffer to the
internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the
programmed threshold level, the RTL8139C(L) begins packet transmission.
9.2 Receive Operation
The incoming packet is placed in the RTL8139C(L)'s Rx FIFO. Concurrently, the RTL8139C(L) performs address filtering of
multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches the level defined in the
Receive Configuration Register, the RTL8139C(L) requests the PCI bus to begin transferring the data to the Rx buffer in PCI bus
master mode.
9.3 Line Quality Monitor
The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount of Equalization being used
by accessing certain test registers with the DSP engine. This provides a crude indication of connected cable length. This function
allows for a quick and simple verification of the line quality in that any significant deviation from an expected register value (based on
a known cable length) would indicate that the signal quality has deviated from the expected nominal case.
9.4 Clock Recovery Module
The Clock Recovery Module (CRM) is supported in both 10Base-T and 100Base-TX mode. The CRM accepts 125Mb/s MLT3 data
from the equalizer. The DPLL locks onto the 125Mb/s data stream and extracts a 125MHz recovered clock. The extracted and
synchronized clock and data are used as required by the synchronous receive operations.
9.5 Loopback Operation
Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function correctly. In loopback mode for
100Mbps, the RTL8139C(L) takes frames from the transmit descriptor and transmits them up to internal Twister logic.
9.6 Tx Encapsulation
While operating in 100Base-TX mode, the RTL8139C(L) encapsulates the frames that it transmits according to the 4B/5B
code-groups table. The changes of the original packet data are listed as follows:
1. The first byte of the preamble in the MAC frame is replaced with the JK symbol pair.
2. After the CRC, the TR symbol pair is inserted.
9.7 Collision
If the RTL8139C(L) is not in full-duplex mode, a collision event occurs when the receive input is not idle while the
RTL8139C(L) transmits. If the collision was detected during the preamble transmission, the jam pattern is transmitted after
completing the preamble (including the JK symbol pair).
相關(guān)PDF資料
PDF描述
RTL8139B REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139D REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8201 REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL
RTL8201BL REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL
RTL8208 REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RTL8139B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8139C_PLUS 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RTL8139C_Plus Specification
RTL8139CL 制造商:Realtek Semiconductor 功能描述:
RTL8139CL+ 制造商:Realtek Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*