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參數資料
| 型號： | RTL8139A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| 中文描述： | 瑞昱單芯片快速以太網控制器電源管理 |
| 文件頁數： | 42/62頁 |
| 文件大?。?/td> | 648K |
| 代理商： | RTL8139A |
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RTL8139C(L)
2002/01/10
Rev.1.4
42
ILR:
Interrupt Line Register
The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the
POST software to set interrupt line for the RTL8139C(L).
IPR:
Interrupt Pin Register
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8139C(L). The
RTL8139C(L) uses INTA interrupt pin. Read only. IPR = 01H.
MNGNT:
Minimum Grant Timer: Read only
Specifies how long a burst period the RTL8139C(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This
field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
MXLAT:
Maximum Latency Timer: Read only
Specifies how often the RTL8139C(L) needs to gain access to the PCI bus in units of 1/4 microseconds. This field
will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
8.3 Default Values After Power-on (RSTB asserted)
PCI Configuration Space Table
No.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
|
27h
Name
VID
DID
Command
Status
Revision ID
PIFR
SCR
BCR
CLS
LTR
HTR
BIST
IOAR
MEMAR
-
Type
R
R
R
R
R
W
R
W
R
R
W
R
R
R
R
R
R
W
R
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit7
1
0
0
1
0
-
0
-
0
0
DPERR
0
0
0
0
0
0
LTR7
0
0
0
0
0
0
0
0
0
0
Bit6
1
0
0
0
0
PERRSP
0
-
0
0
SSERR
0
0
0
0
0
0
LTR6
0
0
0
0
0
0
0
0
0
0
Bit5
1
0
1
0
0
-
0
-
0
0
RMABT
0
0
0
0
0
0
LTR5
0
0
0
0
0
0
0
0
0
0
Bit4
0
1
0
0
0
-
0
-
NewCap
0
RTABT
0
0
0
0
0
0
LTR4
0
0
0
0
0
0
0
0
0
0
Bit3
1
0
1
0
0
-
0
-
0
0
STABT
0
0
0
0
0
0
LTR3
0
0
0
0
0
0
0
0
0
0
Bit2
1
0
0
0
0
BMEN MEMEN
0
-
0
0
-
0
0
0
0
0
0
LTP2
0
0
0
0
0
0
0
0
0
0
Bit1
0
0
0
0
0
Bit0
0
0
1
1
0
IOEN
0
SERREN
0
0
DPD
0
0
0
0
0
0
LTR0
0
0
1
0
0
0
0
0
0
0
0
-
0
1
-
0
0
0
1
0
0
LTR1
0
0
0
0
0
0
0
0
0
0
RESERVED(ALL 0)
0
0
28h
29h
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CISPtr
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