參數(shù)資料
型號: S1C621A0F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 116/161頁
文件大?。?/td> 1037K
代理商: S1C621A0F0A0100
S1C621A0 TECHNICAL HARDWARE
EPSON
I-33
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
Timer counter timing chart (low-order)
Frequency
Data
Address
0F4H
D0
128 Hz
D1
D2
D3
64 Hz
32 Hz
16 Hz
32 Hz interrupt request
Timer counter timing chart (high-order)
Frequency
0F5H
D3
16 Hz
D0
D1
D2
8 Hz
4 Hz
2 Hz
32 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
D3
1 Hz
0F4H
Data
Address
The timer sets an interrupt factor flag (the low-order three
bits of address 0F1H: TI32, TI8, TI2) to 1 at the falling edge
of a 32 Hz, 8 Hz or 2 Hz signal, thus generating an interrupt
request signal to the CPU. The interrupt request signal can
be masked for each frequency using the low-order three bits
of address 0F3H. In other words, ETI32, ETI8 and ETI2
enable or disable a 32 Hz interrupt request, an 8 Hz inter-
rupt request and a 2 Hz interrupt request, respectively. The
interrupt factor flag is a read-only register. When it is read,
its contents are cleared to 0. Read this register in DI status
(interrupt flag = 0). Reading of interrupt factor flags is avail-
able at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated. Be very
careful when interrupt factor flags are in the same address.
At initial reset, all of the 32 Hz, 8 Hz and 2 Hz interrupt
requests are disabled.
Timer interrupt
request
Fig. 3.8.1
Timing Chart of Timer
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