參數(shù)資料
型號: S1C621A0F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 31/161頁
文件大小: 1037K
代理商: S1C621A0F0A0100
127
32000D–04/2011
AVR32
ADD– Add without Carry
Architecture revision:
Architecture revision1 and higher.
Description
Adds the two registers specified and stores the result in destination register. Format II allows
shifting of the second operand.
Operation:
I.
Rd
← Rd + Rs;
II.
Rd
← Rx + (Ry<< sa2);
Syntax:
I.
add
Rd, Rs
II.
add
Rd, Rx, Ry << sa
Operands:
I.
{d, s}
∈ {0, 1, …, 15}
II.
{d, x, y}
∈ {0, 1, …, 15}
sa
∈ {0, 1, 2, 3}
Status Flags
Format I: OP1 = Rd, OP2 = Rs
Format II:OP1 = Rx, OP2 = Ry << sa2
Q:
Not affected
V:
V
← (OP1[31] ∧ OP2[31] ∧ RES[31]) ∨ (OP1[31] ∧ OP2[31] ∧ RES[31])
N:
N
← RES[31]
Z:
Z
← (RES[31:0] == 0)
C:
C
← OP1[31] ∧ OP2[31] ∨ OP1[31] ∧ RES[31] ∨ OP2[31] ∧ RES[31]
Opcode:
Format I:
Format II:
000
Rs
00000
Rd
15
13
12
9
8
4
3
0
111
Rx
00000
Ry
31
29
28
25
24
20
19
16
0000000000
Shift Amount
Rd
15
12
11
8
7
6
5
4
3
0
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