參數(shù)資料
型號: S1C621A0F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 147/161頁
文件大?。?/td> 1037K
代理商: S1C621A0F0A0100
S1C621A0 TECHNICAL HARDWARE
EPSON
I-61
CHAPTER 3: PERIPHERAL CIRCUITS (Initial Reset)
The RESET signal directly initializes the S1C621A0. The
system is reset when RESET = 0, and released from the
reset state when RESET = 1. As the RESET pin is pulled up
and receives a Schmitt trigger input, it can be used as a
power-on clear circuit if the RESET pin is connected with
the VSS pin via a capacitor as shown in Figure 3.12.3. A
reset switch must be provided (see Figure 3.12.3) to obtain
an assured reset effect at power-on without being influenced
by possible power. This is especially important for a reset
operation without the use of the OSC3 oscillation circuit, in
which case the system clock (OSC1) must be ON before the
system is released from the reset state.
RESET
Fig. 3.12.3
Power-on Clear Circuit
To reset circuit
C
RESET
SR
S1C621A0
VDD
VSS
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