參數(shù)資料
型號: S1C621A0F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 142/161頁
文件大小: 1037K
代理商: S1C621A0F0A0100
S1C621A0 TECHNICAL HARDWARE
EPSON
I-57
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Interrupt mask
register
One interrupt mask register is available to each interrupt
factor flag to mask an interrupt request. Data can be written
to or read from the mask register. An interrupt request is
enabled with 1 set in the register, and masked with 0 set in
the register. (See Figure 3.11.4.) At initial reset, the mask
register is reset to 0.
Table 3.11.3
Interrupt Mask Register
In response to an interrupt request, the CPU starts interrupt
processing. The CPU saves the PC into the stack and makes
a jump to the interrupt address, that is the interrupt han-
dling routine. The interrupt address is indirectly specified by
an interrupt factor. Interrupt addresses are assigned to page
1, steps 01H to 0FH of the PC. In other words, the low-order
4 bits of the PC are indirectly addressed by interrupt factors,
as follows:
Interrupt vector
ETI2
ETI8
ETI32
EIREM
EIK1
EIK0
Name
0F3H
0F2H
Address
D2
D1
D0
D2
D1
D0
Data bit
Interrupt mask register
TI2
TI8
TI32
IREM
IK1
IK0
Name
0F1H
0F0H
Address
D2
D1
D0
D2
D1
D0
Data bit
Interrupt factor flag
PCS3
PCS2
PCS1
PCS0
PC
1
0
1
0
1
0
1
0
Value
Timer interrupt requested
Timer interrupt not requested
REM interrupt requested
REM interrupt not requested
K10–K13 interrupt requested
K10–K13 interrupt not requested
K00–K03 interrupt requested
K00–K03 interrupt not requested
Interrupt factor
Table 3.11.4
Interrupt Vector
Examples
Only timer interrupt requested
— Jump to page 1, step 08H
Both timer interrupt and REM interrupt requested
— Jump to page 1, step 0CH
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