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參數(shù)資料
| 型號(hào)： | SAA2502 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ISO/MPEG Audio Source Decoder |
| 中文描述： | 的ISO / MPEG音頻信源解碼器 |
| 文件頁數(shù)： | 15/64頁 |
| 文件大?。?/td> | 318K |
| 代理商： | SAA2502 |
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1997 Nov 17
15
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7.3.3
B
UFFER CONTROLLED INPUT MODE
(see Fig.10)
Buffer controlled input mode is activated by setting the
INMOD control flags to 1X, which means that the SAA2502
will request data based on the amount of input bytes
currently residing in the input buffer.
The bit clock CDCL is output, its frequency is fixed:
when MCLK24 = logic 1
when MCLK24 = logic 0.
In this mode CDRQ = logic 1 is an indication that new input
data is required. CDVAL = logic 1 indicates the delivery of
valid data. The application should react to the event of an
input data request as follows:
One byte of input data should be delivered within
16 CDCL cycles. If CDRQ remains high the next byte
32
MCLK
16
MCLK
should be delivered and so on until CDRQ is dropped.
Delivery of subsequent bytes while CDRQ remains
HIGH should be uninterrupted (CDVAL should stay
HIGH)
There is also an option for the application to deliver part
of the input data later. Despite violating the conditions in
the previous paragraph, this is allowed, but with
consequences for the input buffer latency time.
MPEG free format bit rate is allowed in this mode.
Dynamically varying bit rate may be supported in this
mode. Whether such support is desired or not is indicated
by the following input mode bits:
INPMOD = 10 means bit rate is assumed to be (quasi)
static
INPMOD = 11 means bit rate is assumed to be dynamic.
Fig.10 Buffer controlled mode input data format.
handbook, full pagewidth
MGE477
CDCL
CD
CDEF
CDRQ
CDVAL
CDSY
unreliable data bit (example)
start of byte or frame
valid data
valid but unreliable data
invalid data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA2502H | ISO/MPEG Audio Source Decoder |
| SAA2503 | MPEG2 audio decoder(MPEG2 音頻譯碼器) |
| SAA2503HT | MPEG2 audio decoder |
| SAA2505H-M1 | Digital multi-channel audio IC DUET |
| SAA2505 | Digital multi-channel audio IC DUET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2502H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/MPEG Audio Source Decoder |
| SAA2503 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2503HT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2505 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2505H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
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