參數(shù)資料
型號(hào)： SAA2502
廠商： NXP Semiconductors N.V.
英文描述： ISO/MPEG Audio Source Decoder
中文描述： 的ISO / MPEG音頻信源解碼器
文件頁(yè)數(shù)： 9/64頁(yè)
文件大?。?/td> 318K
代理商： SAA2502
1997 Nov 17
9
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7.2.3
L
OCKED INTERNAL SAMPLE CLOCK
This mode differs from the previous one in just a single
aspect: the REFCLK and PHDIF pins are used to realize a
Phase-Locked Loop (PLL) which locks the 256
×
f
s
sample
clock to the REFCLK reference clock. Because the real
goal is locking sample clock and bit rate, a reference clock
should be used which has a fixed relation to the input bit
rate. An example of such a PLL realization is shown in
Fig.4.
The phase comparator output PHDIF generates a signal
with a DC component proportional to the phase difference
between the internal signals SIG and REF (see Fig.5).
The 22.5792 MHz signal X22IN is divided by 147 and the
24.576 MHz signal MCLKIN is divided by 160. This results
in the same frequency (153.6 kHz) in both events.
One of the two signals is selected as input for the
programmable divide by N
1
unit. The selector is controlled
handbook, halfpage
MGE470
C1
C3
C4
X1
X2
R1
R4
R2
R3
26
27
32
31
SAA2502
Fig.3 Crystal oscillator components.
C1 = C2 = C3 = C4 = 10 pF;
R1 = R4 = 100 k
;
R2 = R3 = 1 k
;
X1 = 22.5792 MHz;
X2 = 24.5760 MHz.
in such a way that SIG and 256
×
f
s
will stem from the
same source. The divisor N
1
is programmable with
(1 to 16)
×
8 as possible values.
REF on the other hand is derived from the REFCLK input.
Two programmable dividers in series are used here. N
2
may adopt one of 4 possible values: 5, 25, 125 or 625
while N
3
can be programmed to be 1 to 32. Because both
inputs of the phase comparator have to operate at identical
frequencies the next equation has to be obeyed:
or, written differently:
For a list of supported REFCLK frequency values
see Chapter 8.
The mode of operation of the phase comparator in Fig.5 is
programmable via the control flag PHSMOD:
2
N
3
×
N
1
156N
=
REFCLK
153.6 kHz
-----------------------------------------------------
N
×
N
3
×
N
1
=
Fig.4 External PLL components.
handbook, halfpage
MGE471
LOW-
PASS
FILTER
24.576 MHz
VCXO
22.5792 MHZ
VCXO
PHDIF
MCLKIN
MCLKOUT
X22IN X22OUT
SAA2502
Fig.5 SAA2502 phase comparator.
handbook, full pagewidth
MGE472
DIVIDE BY
147
DIVIDE BY
160
DIVIDE BY
N2
DIVIDE BY
N3
DIVIDE BY
N1
PHASE
COMPA-
RATOR
X22IN
MCLKIN
REFCLK
153.6 kHz
SIG
REF
PHDIF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA2502H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/MPEG Audio Source Decoder
SAA2503 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder
SAA2503HT 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder
SAA2505 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET
SAA2505H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET
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