參數(shù)資料
型號(hào): SAA2502
廠商: NXP Semiconductors N.V.
英文描述: ISO/MPEG Audio Source Decoder
中文描述: 的ISO / MPEG音頻信源解碼器
文件頁數(shù): 34/64頁
文件大?。?/td> 318K
代理商: SAA2502
1997 Nov 17
34
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
Table 28
Explanation of bits in Tables 26 and 27
Note
1.
Default settings (settings value after a hard reset).
7.6.6.3
Input and decoding control
Table 29
Input and decoding control: 1 byte (write-only, restricted type, local address = 33H)
BIT
DESCRIPTION
FSCINP
external sample clock mode:
logic 0
(1)
: internal sample clock mode (sample clock derived from MCLKIN and X22IN clock inputs)
logic 1: external sample clock mode (FSCLKIN is sample clock input)
external sample clock frequency indication:
logic 0
(1)
: FSCLKIN is 256
×
f
s
logic 1: FSCLKIN is 384
×
f
s
FSCLK output enable flag:
logic 0
(1)
: FSCLK output is disabled
logic 1: FSCLK output is enabled
phase detector mode of operation:
logic 0
(1)
: edge triggered mode of operation
logic 1: XOR mode of operation
reversed phase detection:
logic 0
(1)
: normal phase detection
logic 1: reversed phase detection (characteristics mirrored with reference to vertical axis)
code for N1 value:
‘0’
(1)
N1 = 8; ‘1’ N1 = 16; ‘2’ N1 = 24; ‘3’ N1 = 32; ‘4’ N1 = 40; ‘5’ N1 = 48; ‘6’ N1 = 56; ‘7’ N1 = 64
code for N2 value:
‘0’
(1)
N2 = 5; ‘1’ N2 = 25; ‘2’ N2 = 125; ‘3’ N2 = 625
N3
1; range 0
(1)
to 31 (N3 is 1 to 32)
FSC384
FSCENA
PHSMOD
PHSRVS
N1b3 to 0
N2b1 to 0
N3b4 to 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SYMOD1
SYMOD0
INMOD1
INMOD0
STOPRQ
CRCACT
SELCH2
SFCRC
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