參數(shù)資料
型號(hào)： SAA2502
廠商： NXP Semiconductors N.V.
英文描述： ISO/MPEG Audio Source Decoder
中文描述： 的ISO / MPEG音頻信源解碼器
文件頁(yè)數(shù)： 17/64頁(yè)
文件大?。?/td> 318K
代理商： SAA2502
1997 Nov 17
17
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7.4.2
M
ASTER INPUT MODE BIT RATE GENERATION
When master input mode is used, the SAA2502 fetches
input data at the effective bit rate. However after a hard
reset the input requests input data at the default bit rate
until synchronization has been established as shown in
Table 7.
When the clock generator mode is ‘free running internal
sample clock’ or ‘locked internal sample clock’ the default
input bit rate is always 384 kbits/s. When the mode is
‘external sample clock’ the SAA2502 derives the selected
bit rate from the signal FSCLKIN. But initially it has no
indication of the current sampling rate corresponding to
FSCLKIN. Therefore the bit rate of 384 kbits/s is
generated at an assumed sampling frequency of 44.1 kHz.
For different sample rates, the bit rate changes
proportionally.
The consequence is that while the SAA2502 is
synchronizing after a hard reset, the application should be
able to supply input data at the given default bit rate until
synchronization is established. Alternatively there is also
the possibility to overrule default bit rate setting and
sample rate setting using the control interface while
synchronization has not been established.
The speed at which input data is requested by the input in
master mode is changed in one of the following events:
When input synchronization is established at the end of
the verification phase and the bit rate index of the
decoded bit stream indicates a bit rate different from the
one currently selected. In this event, the bit rate is
adapted to the new index.
When the signal STOP is raised while the STOPRQ
control flag = logic 1, input requesting is halted.
Requesting resumes at the last selected input bit rate
when the STOP signal is dropped.
In all other events (including when the SAA2502 loses
synchronization), the last selected input bit rate is
maintained.
Whenever the selected bit rate changes while dynamic bit
rate is not enabled, the SAA2502 will generate internally a
soft reset resulting in a soft mute of the output interfaces
and a decoder restart in order to re-initialize internal buffer
settings.
Table 7
Establishment of default bit rate
CLOCK GENERATOR MODE
FSCLKIN (kHz)
DEFAULT BIT RATE (kbits/s)
Free running internal clock
Locked internal clock
External sample clock
don’t care
don’t care
256 or 384
×
48
256 or 384
×
44.1
256 or 384
×
32
256 or 384
×
24
256 or 384
×
22.05
256 or 384
×
16
384
384
417.96
384
278.64
208.98
192
139.32
相關(guān)PDF資料
PDF描述
SAA2502H ISO/MPEG Audio Source Decoder
SAA2503 MPEG2 audio decoder(MPEG2 音頻譯碼器)
SAA2503HT MPEG2 audio decoder
SAA2505H-M1 Digital multi-channel audio IC DUET
SAA2505 Digital multi-channel audio IC DUET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA2502H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ISO/MPEG Audio Source Decoder
SAA2503 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder
SAA2503HT 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder
SAA2505 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET
SAA2505H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET
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