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參數(shù)資料
| 型號： | SAH-C515A-4R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 49/182頁 |
| 文件大?。?/td> | 1917K |
| 代理商： | SAH-C515A-4R |
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Semiconductor Group
8-4
1997-08-01
Fail Safe Mechanisms
C515A
8.1.3 Starting the Watchdog Timer
Immediately after start (see next section for the start procedure), the watchdog timer is initialized to
the reload value programmed to WDTREL.0 - WDTREL.6. After an external HW or HWPD reset, an
oscillator power on reset, or a watchdog timer reset, register WDTREL is cleared to 00H. WDTREL
can be loaded by software at any time.
There are two ways to start the watchdog timer depending on the level applied to pin PE/SWD. This
pin serves two functions, because it is also used for blocking the power saving modes. (see also
chapter 9).
8.1.3.1
The First Possibility of Starting the Watchdog Timer
The automatic start of the watchdog timer directly while an external HW reset is a hardware start
initialized by strapping pin PE/SWD to
V
CC. In this case the power saving modes (power down
mode, idle mode and slow down mode) are also disabled and cannot be started by software. If pin
PE/SWD is left unconnected, a weak pull-up transistor ensures the automatic start of the watchdog
timer.
The self-start of the watchdog timer by a pin option has been implemented to provide high system
security in electrically very noisy environments.
Note: The automatic start of the watchdog timer is only performed if PE/SWD (power-save enable/
start watchdog timer) is held at high level while RESET or HWPD is active. A positive
transition at these pins during normal program execution will not start the watchdog timer.
Furthermore, when using the hardware start, the watchdog timer starts running with its
default time-out period. The value in the reload register WDTREL, however, can be
overwritten at any time to set any time-out period desired.
8.1.3.2
The Second Possibility of Starting the Watchdog Timer
The watchdog timer can also be started by software. Setting of bit SWDT in SFR IEN1 starts the
watchdog timer. Using the software start, the timeout period can be programmed before the
watchdog timer starts running.
Note that once the watchdog timer has been started it can only be stopped if one of the following
conditions are met :
– active external hardware reset through pin RESET with a low level at pin PE/SWD
– active hardware power down signal HWPD, independently of the level at PE/SWD
– entering idle mode or power down mode by software
See chapter 9 for entering the power saving modes by software.
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