參數(shù)資料
型號(hào)： SAH-C515A-4R
廠(chǎng)商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝： METRIC, PLASTIC, QFP-80
文件頁(yè)數(shù)： 50/182頁(yè)
文件大?。?/td> 1917K
代理商： SAH-C515A-4R
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Semiconductor Group
8-5
1997-08-01
Fail Safe Mechanisms
C515A
8.1.4 Refreshing the Watchdog Timer
At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents of
WDTREL.0 to WDTREL.6. Once started the watchdog cannot be stopped by software but can only
be refreshed to the reload value by first setting bit WDT (IEN0.6) and by the next instruction setting
SWDT (IEN1.6). Bit WDT will automatically be cleared during the second machine cycle after
having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g. SETB
SWDT). This double-instruction refresh of the watchdog timer is implemented to minimize the
chance of an unintentional reset of the watchdog.
The reload register WDTREL can be written to at any time, as already mentioned. Therefore, a
periodical refresh of WDTREL can be added to the above mentioned starting procedure of the
watchdog timer. Thus a wrong reload value caused by a possible distortion during the write
operation to the WDTREL can be corrected by software.
8.1.5 Watchdog Reset and Watchdog Status Flag
lf the software fails to clear the watchdog in time, an internally generated watchdog reset is entered
at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler
selection (either 8 cycles or 128 cycles). This internal reset differs from an external one only in so
far as the watchdog timer is not disabled and bit WDTS (watchdog timer status, bit 6 in SFR IP0) is
set. Figure 8-2 shows a block diagram of all reset requests in the C515A and the function of the
watchdog status flags. The WDTS flag is a flip-flop, which is set by a watchdog timer reset and
cleared by an external HW reset. Bit WDTS allows the software to examine from which source the
reset was activated. The watchdog timer status flag can also be cleared by software.
Figure 8-2
Watchdog Timer Status Flags and Reset Requests
MCS02756
WDT Reset Request
IP0 (A9H)
OWDS WDTS
OWD Reset Request
Set
Clear
External HW Reset Request
External HW-Power Down Request
Internal Bus
RESET
HWPD
Synchronization
Reset
Internal
< _ 1
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