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| 型號(hào)： | SAH-C515A-4R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 52/182頁(yè) |
| 文件大?。?/td> | 1917K |
| 代理商： | SAH-C515A-4R |
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Semiconductor Group
8-7
1997-08-01
Fail Safe Mechanisms
C515A
8.2.1 Description of the Oscillator Watchdog Unit
Figure 8-3 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC
oscillator which provides the reference frequency for the comparison with the frequency of the on-
chip oscillator. It also shows the modifications which have been made for integration of the wake-
up from power down mode capability.
Figure 8-3
Functional Block Diagram of the Oscillator Watchdog
The frequency coming from the RC oscillator is divided by 5 and compared to the on-chip oscillator's
frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency
derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip
oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal
clock system to the output of the RC oscillator. This means that the part is being clocked even if the
on-chip oscillator has stopped or has not yet started. At the same time the watchdog activates the
internal reset in order to bring the part in its defined reset state. The reset is performed because
clock is available from the RC oscillator. This internal watchdog reset has the same effects as an
externally applied reset signal with the following exceptions: The Watchdog Timer Status flag
WDTS is not reset (the Watchdog Timer however is stopped); and bit OWDS is set. This allows the
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