參數(shù)資料
型號(hào): SC28C94A1A,518
廠商: NXP Semiconductors
文件頁數(shù): 21/39頁
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 52-PLCC
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 故障啟動(dòng)位檢測(cè)
通道數(shù): 4,QUART
FIFO's: 8 字節(jié)
電源電壓: 5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 52-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 52-PLCC(19.2x19.2)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-1114-6
Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
28
AC ELECTRICAL CHARACTERISTICS
VCC = 5 V ± 10 %, TA = –40 _C to +85 _C, unless otherwise specified.
NO
FIGURE
CHARACTERISTIC
LIMITS
UNIT
NO.
FIGURE
CHARACTERISTIC
Min
Typ
Max
UNIT
1
6
D[7:0] Valid after IACKN Low
65
ns
2
6
DACKN Low after IACKN Low
0 + 2
X1 edges1
30 + 3
X1 edges1
ns
3
6
D[7:0] floating after IACKN High
0
15
ns
4
6
DACKN High after IACKN High
0
15
ns
5
6
IACKN High after IACKN Low
30
ns
NOTE:
1. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges
in the ‘X1/CLK divide by 2 edges’ according to register 2Eh or 2Fh setting.
IRQN
IACKN
D[7:0]
DACKN
1
5
2
3
4
SD00165
NOTE: Rise time of IRQN is dependent on external circuit.
Figure 6. Interrupt Knowledge (IACKN) Timing
OSC/N
EVAL/HOLD
IACKN
CIR
VALUE FOR THIS INTERRUPT
SD00166
Figure 7. Interrupt Bid Arbitration Timing
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