參數(shù)資料
型號(hào)： SC28C94A1A,518
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 8/39頁(yè)
文件大?。?/td> 0K
描述： IC UART QUAD W/FIFO 52-PLCC
產(chǎn)品培訓(xùn)模塊： Stand-Alone UARTs
標(biāo)準(zhǔn)包裝： 1
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 4，QUART
FIFO's： 8 字節(jié)
電源電壓： 5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 52-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 52-PLCC（19.2x19.2）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 828 (CN2011-ZH PDF)
其它名稱： 568-1114-6
Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
16
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected, the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes; if the
deselection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop bit has been retransmitted.
MR2[5] – Transmitter Request-to-Send Control
NOTE: When the transmitter controls the I/O2 pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather it signals that the transmitter has finished transmission.
(i.e., end of block).
This bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2[5] = 1
causes RTSN to be reset automatically one bit time after the
characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission as follows:
1. Program auto-reset mode: MR2[5] = 1.
2. Enable transmitter.
3. Assert RTSN via command.
4. Send message.
5. Disable the transmitter after the last byte of the message is
loaded to the TxFIFO. At the time the disable command is
issued, be sure that the transmitter ready bit is on and the
transmitter empty bit is off. If the transmitter empty bit is on (the
indication of transmitter underrun) when the disable is issued,
the last byte(s) will not be sent.
6. The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
MR2[4] – Transmitter Clear-to-Send Flow Control
The sate of this bit determines if the CTSN input (I/O0) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the sate of CTSN
each time it is ready to send a character. If it is asserted (Low), the
character is transmitted. If it is negated (High), the TxD output
remains in the marking state and the transmission is delayed until
CTSN goes Low. Changes in CTSN, while a character is being
transmitted do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1–1/16 to
2 stop bits can be programmed in increments of 1/16 bit. If an
external 1X clock is used for the transmitter, MR2[3] = 0 selects one
stop bit and MR2[3] = 1 selects two stop bits to be transmitted.
RECEIVER NOTE: In all cases, the receiver only checks for a
“mark” condition at the center of the stop bit (1/2 to 9/16 bit
time into the stop bit position). At this time the receiver has
finished processing the present character and is ready to
search for the start bit of the next character.
Table 5. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
NORMAL RATE
(BAUD)
ACTUAL 16X
CLOCK (kHz)
ERROR (%)
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
7200
9600
19.2K
38.4K
0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
16.756
19.2
28.8
32.056
38.4
76.8
115.2
153.6
307.2
614.4
0
-0.069
0.059
0
-0.260
0
0.175
0
NOTE: Duty cycle of 16X clock is 50%
± 1%.
CR – Command Register
CR is used to write commands to the QUART.
CR[7:4] – Miscellaneous Commands
Issuing commands contained in the upper four bits of the “Command
Register” should be separated in time by at least three (3) X1 clock
edges. Allow four (4) edges if the “X1 clock divide by 2” mode is
used. The encoded value of this field can be used to specify a single
command as follows:
0000
No command.
0001
Reset MR pointer. Causes the MR pointer to point to MR1.
0010
Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location.
0011
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
0100
Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]}. Used in character mode to clear OE status
(although RB, PE, and FE bits will also be cleared), and in
block mode to clear all error status after a block of data
has been received.
0101
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2 or 6]) to
be cleared to zero.
0110
Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active, the
break begins when transmission of the character is
completed. If a character is in the TxFIFO, the start of break
is delayed until that character or any others loaded after it
have been transmitted (TxEMT must be true before break
begins). The transmitter must be enabled to start a break
0111
Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the
next character, if any, is transmitted.
1000
Assert RTSN. Causes the RTSN output to be asserted
(Low).
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