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參數(shù)資料
| 型號： | SC28C94A1A,518 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 3/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART QUAD W/FIFO 52-PLCC |
| 產(chǎn)品培訓模塊： | Stand-Alone UARTs |
| 標準包裝： | 1 |
| 特點： | 故障啟動位檢測 |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 8 字節(jié) |
| 電源電壓： | 5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 52-PLCC（19.2x19.2） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 828 (CN2011-ZH PDF) |
| 其它名稱： | 568-1114-6 |
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Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
11
Functional Description of the Interrupt Arbitration
For the purpose of this description, a ‘source’ is any one of the 18
QUART circuits that may generate an interrupt. The QUART
contains eighteen sources which may cause an interrupt:
1. Four receiver data FIFO filled functions.
2. Four receiver BREAK detect functions.
3. Four transmitter FIFO space available functions.
4. Four “Change of State” detectors.
5. Two counter/timers.
The interrupt logic at each source produces a numeric code that
identifies its interrupt priority condition currently pending. This code
is compared to a programmable Interrupt Threshold via the
arbitration logic which determines if the IRQN should be asserted.
The arbitration logic only judges those possible interrupt sources
which have been allowed to bid via the IMR (Interrupt Mask
Register).
The arbitration logic produces a value which is the concatenation of
the channel number, interrupt type, FIFO fill level and user-defined
fields. The channel number and interrupt type fields are hardwired.
During the “bid arbitration” process all bids from enabled sources
are presented, simultaneously, to an internal interrupt bus. The
bidding system and formats are discussed in more detail in
following sections.
The interrupt arbitration logic insures that the interrupt with the
numerically largest bid value will be the only source driving the
interrupt bus at the end of the arbitration period. The arbitration
period follows the period of the X1 clock. The maximum speed is
4.0MHz. If a higher speed X1 clock is used then the X1 clock “divide
by 2” feature must be used.
The value of the winning bid determined during the arbitration cycle
is compared to the “Interrupt Threshold” contained in the ICR
(Interrupt Control Register). If the winning bid exceeds the value of
the ICR the IRQN is asserted.
Priority Arbitration and Bidding
Each of the five “types” of interrupts has slightly different “bid” value,
as follows:
Receivers
Transmitters
Break Detect
Change of State
Counter/Timer
# rcv’d
rEr
1
Chan #
31
1
2
0
# avail
1
0
Chan #
13
1
2
Programmable
1
0
Chan #
31
1
2
Programmable
0
1
Chan #
31
1
2
Programmable
1
0
1
Chan #
21
1
2
0
1
SD00162
Please see “Interrupt Notes” at the end of this specification.
Bits shown above as ‘0’ or ‘1’ are hard-wired inputs to the arbitration
logic. Their presence allows determination of the interrupt type and
they insure that no bid will have a value of all zeros (a condition that
is indistinguishable from not bidding at all). They also serve to set a
default priority among the non-receive/transmit types when the
programmable fields are all zeros.
The channel number always occupies the two LSBs. Inclusion of
the channel number insures that a bid value generated will be
unique and that a single “winner” will drive the Interrupt Bus at the
end of the arbitration interval. The channel number portion of each
UARTs bid is hard-wired with UARTa being channel number 0 and
so forth.
As can be seen above, bits 4:2 of the winning bid value can be used
to identify the type of interrupt, including whether data was received
correctly or not. Like the Channel number field, these bits are
hard-wired for each interrupt source.
The “# rcv’d” and “# avail” fields indicate the number of bytes
present in the receiver FIFO and the number of empty bytes in the
transmitter FIFO, respectively.
NOTE: When there are zero bytes in the receiver’s FIFO, it does
NOT bid. Similarly, a full transmitter FIFO makes NO bid. In the
case where all bids have been disabled by the Interrupt Mask
Register or as a result of their byte counts, the active-low Interrupt
Bus will return FFh. This value always indicates no interrupt source
is active and IRQN will be negated.
The high order bit of the transmitter “bid” is always zero. An empty
transmit FIFO is, therefore, fixed at a lower interrupt priority than a
1/2 full receive FIFO. Bit 4 of a receiver bid is the Receiver Error Bit
(RER). The RER is the OR of the parity, framing and overrun error
conditions. The RER does little to modify the priority of receiver
interrupts vs. transmitter interrupts. It is output to the Interrupt Bus
to allow inclusion of good data vs. problem data information in the
Current Interrupt Register.
The high order bits of bids for received break, CoS (Change of
State) and Counter/Timer events are all programmable. By
programming ones in these fields, the associated interrupt source
can be made more significant than most receiver and all transmitter
interrupts. Values near zero in these fields makes them lower
priority classes of interrupt.
The channel address for C/T ab will be encoded as channel B (01)
The channel address for C/T cd will be encoded as channel D (11)
As shown in Figure 7, the bid arbitration process is controlled by the
EVAL/HOLDN signal derived from the oscillator clock.
Receipt of an IACKN signal from the host MPU latches the latest
“winning bid” from the latched Interrupt Bus into the Current Interrupt
Register (CIR). This logic is diagrammed in Figure 8.
If the IACKN falling edge of Figure 7 occurs during EVAL time, the
result from the last arbitration (captured by the Interrupt Bus latches)
is stored in CIR. Otherwise, the next EVAL pulse is inhibited and the
value in the Interrupt Bus Latches is stored in CIR.
Clearing the Interrupt
Activities which change the state of the ISR will cause the IRQN to
assert or negate. In addition, the accessing of a global or local
RxFIFO or TxFIFO reduces the associated byte count for transmitter
and receiver data interrupts. If the byte count falls below the
threshold value, the interrupt request is withdrawn. Other interrupt
conditions are cleared when the interrupting source is cleared.
Once the interrupt is cleared, the programmable value lowered or its
byte count value reduced by one of the methods listed above, a
different bidder (or no bidder at all) will win the on-going arbitration.
When the winning bid drops below the Interrupt Threshold
Register’s value, the IRQN pin will negate.
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