參數(shù)資料
型號： SI4136M-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 11/34頁
文件大小： 0K
描述： BOARD EVALUATION FOR SI4136
標(biāo)準(zhǔn)包裝： 1
類型： 合成器
適用于相關(guān)產(chǎn)品： SI4136
已供物品： 板，CD
其它名稱： 336-1119
Si4136/Si4126
Rev. 1.41
19
(Register 0) can be set to 1 to reduce the bias currents
and therefore reduce the power dissipated by the IF
amplifier. For loads less than 500
LPWR should be
set to 0 to maximize the output level.
For IF frequencies greater than 500 MHz, a matching
network is required in order to drive a 50
load. See
below.
The
value
of
LMATCH can be
determined by Table 9.
Typical values range between 8 nH and 40 nH.
Figure 15. IF Frequencies > 500 MHz
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200
resistive load or higher. For
resistive loads greater than 500
(f < 500 MHz) the
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 16 below.
Figure 16. IF Frequencies < 500 MHz
Figure 17. Typical IF Output Voltage vs.
Load Resistance at 550 MHz
2.7. Reference Frequency Amplifier
The Si4136 provides a reference frequency amplifier. If
the driving signal has CMOS levels, it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be AC coupled to the XIN pin
through a 560 pF capacitor.
2.8. Powerdown Modes
Table 10 summarizes the powerdown functionality. The
Si4136 can be powered down by taking the PWDN pin
low or by setting bits in the Powerdown register
(Register 2). When the PWDN pin is low, the Si4136 will
be powered down regardless of the Powerdown register
settings.
When
the
PWDN
pin
is
high,
power
management is under control of the Powerdown register
bits.
The IF and RF sections of the Si4136 circuitry can be
individually powered down by setting the Powerdown
register bits PDIB and PDRB low. The reference
frequency amplifier will also be powered up if either the
PDRB and PDIB bits are high. Also, setting the
AUTOPDB bit to 1 in the Main Configuration register
(Register 0) is equivalent to setting both bits in the
Powerdown register to 1.
The serial interface remains available and can be
written in all power-down modes.
2.9. Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the
AUXSEL bits to 011. This signal can be used to indicate
that the IF or RF PLL is about to lose lock due to
excessive ambient temperature drift and should be re-
tuned.
Table 9. LMATCH Values
Frequency
LMATCH
500–600 MHz
40 nH
600–800 MHz
27 nH
800–1 GHz
18 nH
IFO UT
L
MATCH
>500 pF
50
IFO UT
>500 pF
>200
0
50
100
150
200
250
300
350
400
450
0
200
400
600
800
1000
1200
Load Resistance (
)
Output
Voltage
(mVrms)
LPWR=0
LPWR=1
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