參數(shù)資料
型號(hào)： SI5364-H-GL
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 11/38頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK SONET/SDH PORT 99LFBGA
標(biāo)準(zhǔn)包裝： 168
系列： DSPLL®
類(lèi)型： 時(shí)鐘發(fā)生器，扇出緩沖器（分配）
PLL： 是
輸入： 時(shí)鐘
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 3:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 675MHz
除法器/乘法器： 無(wú)/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -20°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 99-LBGA
供應(yīng)商設(shè)備封裝： 99-BGA（11x11）
包裝： 托盤(pán)
Si5364
Rev. 2.5
19
.
Figure 11. Si5364 State Diagram for Input
Switching
2.5.4. Manual Switching
Manual switching is selected when the AUTOSEL input
is low and is controlled by the MANCNTRL[1:0] inputs.
When these inputs are set to manually select an input
reference, the DSPLL circuitry locks to the selected
clock. If the selected input is in a LOS alarm state, the
PLL goes into digital hold mode. FOS alarms are
declared according to device specifications but have no
automatic effect on clock selection in manual mode. The
MANCNTRL inputs are ignored when the AUTOSEL
input is high.
2.5.5. Digital Hold of the PLL
In digital hold mode, the Si5364 digitally holds the
internal oscillator at its last frequency value to provide a
stable clock output frequency until an input clock is
again valid. The clock maintains very stable operation in
the presence of constant voltage and temperature. The
frequency accuracy specifications for digital hold mode
are given in Table 4 on page 9.
2.5.6. Hitless Recovery from Digital Hold in Manual
Switching Mode
When operating in manual switching mode with the
Si5364 locked to the selected input clock signal, a loss
of the input clock causes the device to automatically
switch to digital hold mode. If the MANCNTRL[1:0] pins
remain stable (the lost clock is still selected), when the
input clock signal returns, the device performs a hitless
transition from digital hold mode back to the selected
input clock. That is, the device performs “phase build-
out” to absorb the phase difference between the internal
VCO clock operating in digital hold mode and the new/
returned input clock.
The hitless recovery feature can be disabled by
asserting the FXDDELAY pin. When the FXDDELAY pin
is high, the output clock is phase and frequency locked
with a fixed-phase relationship to the input clock.
Consequently, abrupt phase changes on the input clock
will propagate through the device and cause the output
to slew at the selected loop bandwidth until the original
phase relationship is restored.
2.5.7. Clock Input to Clock Output Delay Adjustment
The INCDELAY and DECDELAY pins adjust the phase
of
the
Si5364
clock
outputs.
Adjustment
is
accomplished by driving a pulse (a transition from low to
high and then back to low) into one of these pins as the
other pin is held at a logic low level.
Each pulse on the INCDELAY pin adds a fixed delay to
the Si5364’s clock outputs. The amount of delay time is
equal to twice the period of the 622 MHz output clock
(tDELAY =2/fO_622).
Each pulse on the DECDELAY pin removes a fixed
amount of delay from the Si5364’s clock outputs. The
fixed delay time is equal to twice the period of the
622 MHz output clock (tDELAY =2/fO_622).
The frequency of the 622 MHz output clock (fO_622) is
nominally 32x the frequency of the input clock. The
frequency of the 622 MHz output clock (fO_622) is scaled
according to the setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is adjusted
using the INCDELAY and/or DECDELAY pins, the
output clock moves to its new phase setting at a rate of
change that is determined by the setting of the
BWSEL[1:0] pins.
Note:
INCDELAY and DECDELAY are ignored when the
Si5364 operates in digital hold (DH) mode.
A_ACTV=1
B_ACTV=1
F_ACTV=1
DH_ACTV=1
[0,x,x]
[1,0,x]
[1,1,0]
[0,x,x]
[1,0,x]
[0,x,x]
[1,0,x]
[1,1,0]
A_ACTV=1
B_ACTV=1
F_ACTV=1
DH_ACTV=1
[0,x,x]
[x,0,x]
[x,x,0]
[0,1,x]
[1,0,x]
[0,x,1]
[1,0,1]
[1,1,0]
Non-revertive Mode
Revertive Mode
[1,1,1]
[1,0,x]
[0,x,x]
[1,1,0]
[1,1,1]
[0,x,x]
[1,0,x]
[1,1,0]
Notes:
Criteria to determine input switch: [A_fail, B_fail,
LOS_F] where: A_fail = LOS_A or [FOS_A and
(not LOS_F)], B_fail = LOS_B or [FOS_B and (not
LOS_F)]
When entering the DH_ACTV state, the previously
asserted A_ACTV, B_ACTV, or F_ACTV flag
remains asserted.
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