參數(shù)資料
型號： SI5364-H-GL
廠商： Silicon Laboratories Inc
文件頁數(shù)： 9/38頁
文件大?。?/td> 0K
描述： IC CLOCK SONET/SDH PORT 99LFBGA
標準包裝： 168
系列： DSPLL®
類型： 時鐘發(fā)生器，扇出緩沖器（分配）
PLL： 是
輸入： 時鐘
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 3:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 675MHz
除法器/乘法器： 無/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -20°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 99-LBGA
供應(yīng)商設(shè)備封裝： 99-BGA（11x11）
包裝： 托盤
Si5364
Rev. 2.5
17
2.3. Frequency Offset and Loss-of-Signal
Alarms
The Si5364 monitors the input clock signals and
provides alarm output signals for frequency offset and
loss-of-signal that is the basis for manual or automatic
clock input switching decisions.
The frequency offset alarms indicate if the CLKIN_A
and CLKIN_B input clocks are within a specified
frequency precision relative to the frequency of the
REF/CLKIN_F input. The REF/CLKIN_F input can also
be utilized as a third clock input for the DSPLL. The
frequency offset monitoring circuitry compares the
frequency of the CLKIN_A and CLKIN_B input clocks
with the frequency of the supplied reference clock (REF/
CLKIN_F). If the frequency offset of an input clock
exceeds a preset frequency offset threshold, a
frequency offset alarm (FOS) is declared for that clock
input. The frequency offset threshold is selectable for
compatibility with either SONET minimum clock (SMC)
or Stratum 3/3E requirements using the SMC/S3N
control input. Frequency offset threshold values are
indicated in Table 3 on page 8.
2.4. Loss-of-Signal
The Si5364 loss-of-signal (LOS) circuitry constantly
monitors the CLKIN_A, CLKIN_B, and REF/CLKIN_F
input clocks for missing pulses. It over-samples the
input clocks to search for extended periods of time
without clock transitions. If the LOS circuitry detects four
consecutive samples of an input clock that are the same
state (i.e., 1111 or 0000), an LOS is declared for that
input clock. The LOS circuitry runs at a frequency of
f0_622/8, where f0_622 is the output clock frequency when
the FRQSEL[1:0] pins are set to 11. Figure 4 on page 6
and Table 3 on page 8 list the minimum and maximum
transitionless time periods required for declaring an
LOS on an input clock.
Once an LOS flag is asserted on one of the input clocks,
it is held high until the input clock is validated over a
time period designated by the VALTIME pin. When
VALTIME is low, the validation time period is about
100 ms. When VALTIME is high, the validation time
period is about 13 s. If another LOS condition on the
same input clock is detected during the validation time
(i.e., if another set of 1111 or 0000 samples are
detected), the LOS flag remains asserted, and the
validation time starts over.
An LOS alarm on the REF/CLKIN_F clock input
automatically disables the
FOS_A and
FOS_B
frequency offset alarms (frequency offset alarms are
automatically disabled in applications that do not supply
a REF/CLKIN_F input to the Si5364). The FOS_A and
FOS_B frequency offset alarms can be disabled
manually with the DSBLFOS control input.
2.5. Input Clock Select Functions
The Si5364 provides hitless switching between clock
input sources. Switching is controlled automatically or
manually. The criteria for automatic switching are
described below. Automatic switching can be revertive
(returns to the original clock when the alarm condition
clears) or non-revertive. When in manual mode, the
device selects the clock specified by the value of the
MANCNTRL[1:0] inputs.
2.5.1. Hitless Switching
Silicon Laboratories switching technology performs
“phase build-out” to minimize the propagation of phase
transients to the clock outputs during input clock
switching. Many of the problems associated with clock
switching using traditional analog solutions are
eliminated. In the Si5364, all switching between input
clocks occurs within the input multiplexor and DSPLL
phase detector circuitry. The phase detector circuitry
continually monitors the phase difference between each
input clock and the DSPLL VCO clock output. The
phase detector circuitry can lock to a clock signal at a
specified phase offset relative to the VCO output so that
the phase offset is maintained by the DSPLL circuitry. At
the time a clock switch occurs, the phase detector
circuitry
knows
both
the
input-to-output
phase
relationship for the original input clock and of the new
input clock. The phase detector circuitry locks to the
new input clock at the new clock's phase offset so that
the phase of the output clock is not disturbed. That is,
the phase difference between the two input clocks is
absorbed in the phase detector's offset value, rather
than being propagated to the clock output.
The switching technology virtually eliminates the output
clock phase transients traditionally associated with
clock rearrangement (input clock switching). SONET/
SDH specifications allow transients of up to 150 ns of
maximum time interval error (MTIE) to occur during a
Stratum 2/3E clock switch. This specification, which is
sometimes
difficult
to
meet
with
analog
implementations, allows for up to 1500 bit periods of slip
to occur in an OC192 data stream. Silicon Laboratories’
switching eliminates these bit slips and the limitations
imposed by analog methods (such as low bandwidth
loops on the port cards) to meet the SONET/SDH
requirements. The MTIE and maximum slope for clock
output phase transients during clock switching with the
Si5364 are given in Table 4 on page 9. These values fall
significantly below the limits specified in the Telcordia
GR-1244-CORE Requirements.
The characteristic of the phase transient specification is
defined in Figure 10. The clock output phase step
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