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參數(shù)資料
型號(hào): SI5364-H-GL
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 4/38頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK SONET/SDH PORT 99LFBGA
標(biāo)準(zhǔn)包裝: 168
系列: DSPLL®
類型: 時(shí)鐘發(fā)生器,扇出緩沖器(分配)
PLL:
輸入: 時(shí)鐘
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 3:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 675MHz
除法器/乘法器: 無(wú)/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -20°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 99-LBGA
供應(yīng)商設(shè)備封裝: 99-BGA(11x11)
包裝: 托盤
Si5364
12
Rev. 2.5
Clock Output Phase Step Slope3—Manual
Switches
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
mPT
During Clock Switching
6400 Hz
3,200 Hz
1600 Hz
800 Hz
10
5
2.5
1.25
ps/
μs
Clock Output Phase Step Slope3—Auto
Switching
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
mPT
During Clock Switching
6400 Hz
3200 Hz
1600 Hz
800 Hz
36
18
9.0
4.5
ps/
μs
Transient Phase Deviation During Clock
Auto Switching
BWSEL[1:0] = 11
BWSEL[1:0] = 00
BWSEL[1:0] = 01
BWSEL[1:0] = 10
tpt_mtie_max
6400 Hz
3200 Hz
1600 Hz
800 Hz
800
ps
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
3.3 V DC Supply Voltage
VDD33
–0.5 to 3.6
V
LVTTL Input Voltage
VDIG
–0.3 to (+3.6)
V
Maximum Current Any Output PIN
±50
mA
Operating Junction Temperature
TJCT
–55 to 150
°C
Storage Temperature Range
TSTG
–55 to 150
°C
ESD HBM Tolerance (100 pf, 1.5 k
Ω)1.0
kV
Note:
Permanent device damage can occur if the Absolute Maximum Ratings are exceeded. Restrict functional operation to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods might affect device reliability.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
θJA
Still Air
34.9
°C/W
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ± 5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Notes:
1.
Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2.
For reliable device operation, temperature gradients should be limited to 10 °C/min.
3.
Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/
μs unit is used here since the maximum phase transient magnitude
for the Si5364 (tPT_MTIE) never reaches one nanosecond.
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