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參數(shù)資料
| 型號： | SL28EB717ALIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 TNLCRK/TOPCLF 48QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:13 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 166.67MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28EB717
DOC#: SP-AP-0755 (Rev. AA)
Page 2 of 22
32-QFN Pin Definitions
Pin No.
Name
Type
Description
1
GND_SUSPEND
GND
Ground for REF clock and WOL support
2
25MHz
O
25MHz reference output clock
3
VDD_SUSPEND
PWR
3.3V Power Supply for REF clock and power to support WOL
4
CKPWRGD/WOL_STP#/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled /
Asynchronous active low input pin that stops all outputs except free running
25MHz when WOL_EN = “1” (Byte 1 bit 1)
This pin becomes a real-time active low input for asserting power down (PD#)
when WOL_EN = “0” (Byte 1 bit 1).
5
VDD_14
PWR
3.3V Power supply for 14.318MHz clock
6
14.318M / FSC**
I/O, PD Fixed 14.318MHz clock output/3.3V-tolerant input for CPU frequency selection
(internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
7
GND_14
GND
Ground for 14.318MHz clock
8
CLKREQ#1**
I, PD
3.3V clock request input (internal 100K-ohm pull-down)
9
CLKREQ#2**
I, PD
3.3V clock request input (internal 100K-ohm pull-down)
10
PCI0 / SEL_SATA75**
I/O, SE
PD
33MHz clock output/3.3V LVTTL input to enable 75MHz SATA (internal 100K-ohm
pull-down)
0 = SATA75/SRC0 = 100MHz, 1 = SATA75/SRC0 = 75MHz
11
GND_PCI
GND
Ground for PCI clocks
12
VDD_PCI
PWR
3.3V Power supply for PCI clocks
13
PCIF / ITP_EN**
I/O, SE,
PD
33 MHz free running clock output/3.3V LVTTL input to enable SRC6 or CPU2_ITP
(sampled on the CKPWRGD assertion)
0= SRC6, 1= CPU2
14
CLKREQ#3**
I, PD
3.3V clock request input (internal 100K-ohm pull-down)
15
12_48M / SEL12_48*
I/O, SE
PU
12 MHz/ 48MHz Clock output/3.3V-tolerance input for 12MHz or 48MHz selection
(Sampled at CKPWRGD assertion) (internal 100K-ohm pull-up)
0 = 48M, 1 = 12M
16
VDD_48
PWR
3.3V Power supply for 48MHz clocks
17
48M / FSA**
I/O
PD
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection
(internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
18
GND_48
GND
Ground for 48MHz clocks
19
DOT96
O, DIF Fixed true 96MHz clock output
20
DOT96#
O, DIF Fixed complement 96MHz clock output
21
FSB**
I, PD
3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
22
GND_SATA
GND
Ground for SATA clock
23
SATA75M / SRC0
O, DIF 75MHz or 100MHz True differential serial reference clock
24
SATA75M# / SRC0#
O, DIF 75MHz or 100MHz Complement differential serial reference clock
25
VDD_SATA
PWR
3.3V Power supply for SATA clock
26
SRC1
O, DIF 100MHz True differential serial reference clock
27
SRC1#
O, DIF 100MHz Complement differential serial reference clock
28
SRC2
O, DIF 100MHz True differential serial reference clock
29
SRC2#
O, DIF 100MHz Complement differential serial reference clock
30
SRC3
O, DIF 100MHz True differential serial reference clock
31
SRC3#
O, DIF 100MHz Complement differential serial reference clock
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| SL28EB740AZI | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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